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@@ -190,6 +190,7 @@ static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
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/* minimum number of free TX descriptors required to wake up TX process */
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#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
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+#define TG3_TX_BD_DMA_MAX 4096
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#define TG3_RAW_IP_ALIGN 2
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@@ -5940,14 +5941,50 @@ static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
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if (tg3_40bit_overflow_test(tp, map, len))
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hwbug = 1;
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- if (*budget) {
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+ if (tg3_flag(tp, 4K_FIFO_LIMIT)) {
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+ u32 tmp_flag = flags & ~TXD_FLAG_END;
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+ while (len > TG3_TX_BD_DMA_MAX) {
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+ u32 frag_len = TG3_TX_BD_DMA_MAX;
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+ len -= TG3_TX_BD_DMA_MAX;
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+
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+ if (len) {
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+ tnapi->tx_buffers[*entry].fragmented = true;
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+ /* Avoid the 8byte DMA problem */
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+ if (len <= 8) {
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+ len += TG3_TX_BD_DMA_MAX / 2;
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+ frag_len = TG3_TX_BD_DMA_MAX / 2;
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+ }
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+ } else
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+ tmp_flag = flags;
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+
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+ if (*budget) {
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+ tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
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+ frag_len, tmp_flag, mss, vlan);
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+ (*budget)--;
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+ *entry = NEXT_TX(*entry);
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+ } else {
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+ hwbug = 1;
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+ break;
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+ }
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+
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+ map += frag_len;
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+ }
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+
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+ if (len) {
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+ if (*budget) {
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+ tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
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+ len, flags, mss, vlan);
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+ (*budget)--;
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+ *entry = NEXT_TX(*entry);
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+ } else {
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+ hwbug = 1;
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+ }
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+ }
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+ } else {
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tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
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len, flags, mss, vlan);
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- (*budget)--;
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- } else
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- hwbug = 1;
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-
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- *entry = NEXT_TX(*entry);
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+ *entry = NEXT_TX(*entry);
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+ }
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return hwbug;
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}
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@@ -13899,6 +13936,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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if (tg3_flag(tp, 5755_PLUS))
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tg3_flag_set(tp, SHORT_DMA_BUG);
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+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
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+ tg3_flag_set(tp, 4K_FIFO_LIMIT);
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+
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if (tg3_flag(tp, 5717_PLUS))
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tg3_flag_set(tp, LRG_PROD_RING_CAP);
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