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@@ -4680,8 +4680,17 @@ sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
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crtc = intel_get_crtc_for_plane(dev, plane);
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clock = crtc->mode.clock;
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+ if (!clock) {
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+ *sprite_wm = 0;
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+ return false;
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+ }
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line_time_us = (sprite_width * 1000) / clock;
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+ if (!line_time_us) {
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+ *sprite_wm = 0;
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+ return false;
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+ }
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+
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line_count = (latency_ns / line_time_us + 1000) / 1000;
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line_size = sprite_width * pixel_size;
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@@ -6175,7 +6184,7 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
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int i;
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/* The clocks have to be on to load the palette. */
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- if (!crtc->enabled)
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+ if (!crtc->enabled || !intel_crtc->active)
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return;
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/* use legacy palette for Ironlake */
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@@ -6561,7 +6570,7 @@ intel_framebuffer_create_for_mode(struct drm_device *dev,
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mode_cmd.height = mode->vdisplay;
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mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
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bpp);
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- mode_cmd.pixel_format = 0;
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+ mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
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return intel_framebuffer_create(dev, &mode_cmd, obj);
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}
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@@ -8185,7 +8194,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
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if (intel_enable_rc6(dev_priv->dev))
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rc6_mask = GEN6_RC_CTL_RC6_ENABLE |
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- (IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0;
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+ ((IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0);
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I915_WRITE(GEN6_RC_CONTROL,
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rc6_mask |
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