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@@ -529,11 +529,11 @@ static void rv770_gpu_init(struct radeon_device *rdev)
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if (rdev->family == CHIP_RV770)
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gb_tiling_config |= BANK_TILING(1);
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else
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- gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK);
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+ gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
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gb_tiling_config |= GROUP_SIZE(0);
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- if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) {
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+ if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
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gb_tiling_config |= ROW_TILING(3);
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gb_tiling_config |= SAMPLE_SPLIT(3);
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} else {
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@@ -579,14 +579,14 @@ static void rv770_gpu_init(struct radeon_device *rdev)
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/* set HW defaults for 3D engine */
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WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
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- ROQ_IB2_START(0x2b)));
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+ ROQ_IB2_START(0x2b)));
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WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
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WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
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- SYNC_GRADIENT |
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- SYNC_WALKER |
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- SYNC_ALIGNER));
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+ SYNC_GRADIENT |
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+ SYNC_WALKER |
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+ SYNC_ALIGNER));
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sx_debug_1 = RREG32(SX_DEBUG_1);
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sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
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@@ -598,9 +598,9 @@ static void rv770_gpu_init(struct radeon_device *rdev)
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WREG32(SMX_DC_CTL0, smx_dc_ctl0);
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WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
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- GS_FLUSH_CTL(4) |
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- ACK_FLUSH_CTL(3) |
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- SYNC_FLUSH_CTL));
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+ GS_FLUSH_CTL(4) |
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+ ACK_FLUSH_CTL(3) |
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+ SYNC_FLUSH_CTL));
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if (rdev->family == CHIP_RV770)
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WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f));
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@@ -611,12 +611,12 @@ static void rv770_gpu_init(struct radeon_device *rdev)
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}
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WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
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- POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
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- SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
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+ POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
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+ SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
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WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
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- SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
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- SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
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+ SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
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+ SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
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WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
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