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@@ -176,10 +176,10 @@
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/*
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* DMA request assignments
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*/
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-#define MX53_DMA_REQ_SSI3_TX1 47
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-#define MX53_DMA_REQ_SSI3_RX1 46
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-#define MX53_DMA_REQ_SSI3_TX2 45
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-#define MX53_DMA_REQ_SSI3_RX2 44
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+#define MX53_DMA_REQ_SSI3_TX0 47
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+#define MX53_DMA_REQ_SSI3_RX0 46
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+#define MX53_DMA_REQ_SSI3_TX1 45
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+#define MX53_DMA_REQ_SSI3_RX1 44
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#define MX53_DMA_REQ_UART3_TX 43
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#define MX53_DMA_REQ_UART3_RX 42
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#define MX53_DMA_REQ_ESAI_TX 41
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@@ -194,14 +194,14 @@
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#define MX53_DMA_REQ_ASRC_DMA1 32
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#define MX53_DMA_REQ_EMI_WR 31
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#define MX53_DMA_REQ_EMI_RD 30
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-#define MX53_DMA_REQ_SSI1_TX1 29
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-#define MX53_DMA_REQ_SSI1_RX1 28
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-#define MX53_DMA_REQ_SSI1_TX2 27
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-#define MX53_DMA_REQ_SSI1_RX2 26
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-#define MX53_DMA_REQ_SSI2_TX1 25
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-#define MX53_DMA_REQ_SSI2_RX1 24
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-#define MX53_DMA_REQ_SSI2_TX2 23
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-#define MX53_DMA_REQ_SSI2_RX2 22
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+#define MX53_DMA_REQ_SSI1_TX0 29
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+#define MX53_DMA_REQ_SSI1_RX0 28
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+#define MX53_DMA_REQ_SSI1_TX1 27
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+#define MX53_DMA_REQ_SSI1_RX1 26
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+#define MX53_DMA_REQ_SSI2_TX0 25
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+#define MX53_DMA_REQ_SSI2_RX0 24
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+#define MX53_DMA_REQ_SSI2_TX1 23
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+#define MX53_DMA_REQ_SSI2_RX1 22
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#define MX53_DMA_REQ_I2C2_SDHC2 21
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#define MX53_DMA_REQ_I2C1_SDHC1 20
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#define MX53_DMA_REQ_UART1_TX 19
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