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@@ -50,7 +50,7 @@
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#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
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#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
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#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
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#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
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-#define AR7_RESET_PEREPHERIAL 0x0
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+#define AR7_RESET_PERIPHERAL 0x0
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#define AR7_RESET_SOFTWARE 0x4
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#define AR7_RESET_SOFTWARE 0x4
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#define AR7_RESET_STATUS 0x8
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#define AR7_RESET_STATUS 0x8
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@@ -128,7 +128,7 @@ static inline int ar7_has_high_cpmac(void)
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static inline void ar7_device_enable(u32 bit)
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static inline void ar7_device_enable(u32 bit)
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{
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{
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void *reset_reg =
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void *reset_reg =
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- (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
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+ (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
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writel(readl(reset_reg) | (1 << bit), reset_reg);
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writel(readl(reset_reg) | (1 << bit), reset_reg);
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msleep(20);
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msleep(20);
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}
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}
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@@ -136,7 +136,7 @@ static inline void ar7_device_enable(u32 bit)
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static inline void ar7_device_disable(u32 bit)
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static inline void ar7_device_disable(u32 bit)
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{
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{
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void *reset_reg =
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void *reset_reg =
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- (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
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+ (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
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writel(readl(reset_reg) & ~(1 << bit), reset_reg);
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writel(readl(reset_reg) & ~(1 << bit), reset_reg);
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msleep(20);
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msleep(20);
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}
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}
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