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@@ -1190,7 +1190,7 @@ bool ath9k_hw_check_alive(struct ath_hw *ah)
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int count = 50;
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u32 reg;
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- if (AR_SREV_9285_10_OR_LATER(ah))
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+ if (AR_SREV_9285_12_OR_LATER(ah))
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return true;
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do {
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@@ -1787,7 +1787,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
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regulatory->current_rd = eeval;
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eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
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- if (AR_SREV_9285_10_OR_LATER(ah))
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+ if (AR_SREV_9285_12_OR_LATER(ah))
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eeval |= AR9285_RDEXT_DEFAULT;
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regulatory->current_rd_ext = eeval;
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@@ -1893,7 +1893,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
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pCap->num_gpio_pins = AR9271_NUM_GPIO;
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else if (AR_DEVID_7010(ah))
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pCap->num_gpio_pins = AR7010_NUM_GPIO;
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- else if (AR_SREV_9285_10_OR_LATER(ah))
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+ else if (AR_SREV_9285_12_OR_LATER(ah))
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pCap->num_gpio_pins = AR9285_NUM_GPIO;
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else if (AR_SREV_9280_20_OR_LATER(ah))
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pCap->num_gpio_pins = AR928X_NUM_GPIO;
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@@ -2075,7 +2075,7 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
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return MS_REG_READ(AR9271, gpio) != 0;
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else if (AR_SREV_9287_10_OR_LATER(ah))
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return MS_REG_READ(AR9287, gpio) != 0;
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- else if (AR_SREV_9285_10_OR_LATER(ah))
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+ else if (AR_SREV_9285_12_OR_LATER(ah))
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return MS_REG_READ(AR9285, gpio) != 0;
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else if (AR_SREV_9280_20_OR_LATER(ah))
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return MS_REG_READ(AR928X, gpio) != 0;
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