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@@ -121,9 +121,13 @@ void dsp_clk_exit(void)
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for (i = 0; i < DM_TIMER_CLOCKS; i++)
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omap_dm_timer_free(timer[i]);
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+ clk_unprepare(iva2_clk);
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clk_put(iva2_clk);
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+ clk_unprepare(ssi.sst_fck);
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clk_put(ssi.sst_fck);
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+ clk_unprepare(ssi.ssr_fck);
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clk_put(ssi.ssr_fck);
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+ clk_unprepare(ssi.ick);
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clk_put(ssi.ick);
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}
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@@ -145,14 +149,21 @@ void dsp_clk_init(void)
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iva2_clk = clk_get(&dspbridge_device.dev, "iva2_ck");
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if (IS_ERR(iva2_clk))
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dev_err(bridge, "failed to get iva2 clock %p\n", iva2_clk);
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+ else
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+ clk_prepare(iva2_clk);
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ssi.sst_fck = clk_get(&dspbridge_device.dev, "ssi_sst_fck");
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ssi.ssr_fck = clk_get(&dspbridge_device.dev, "ssi_ssr_fck");
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ssi.ick = clk_get(&dspbridge_device.dev, "ssi_ick");
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- if (IS_ERR(ssi.sst_fck) || IS_ERR(ssi.ssr_fck) || IS_ERR(ssi.ick))
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+ if (IS_ERR(ssi.sst_fck) || IS_ERR(ssi.ssr_fck) || IS_ERR(ssi.ick)) {
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dev_err(bridge, "failed to get ssi: sst %p, ssr %p, ick %p\n",
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ssi.sst_fck, ssi.ssr_fck, ssi.ick);
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+ } else {
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+ clk_prepare(ssi.sst_fck);
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+ clk_prepare(ssi.ssr_fck);
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+ clk_prepare(ssi.ick);
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+ }
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}
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/**
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