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@@ -117,18 +117,30 @@ nv84_crypt_tlb_flush(struct drm_device *dev, int engine)
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nv50_vm_flush_engine(dev, 0x0a);
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nv50_vm_flush_engine(dev, 0x0a);
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}
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}
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+static struct nouveau_bitfield nv84_crypt_intr[] = {
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+ { 0x00000001, "INVALID_STATE" },
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+ { 0x00000002, "ILLEGAL_MTHD" },
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+ { 0x00000004, "ILLEGAL_CLASS" },
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+ { 0x00000080, "QUERY" },
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+ { 0x00000100, "FAULT" },
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+ {}
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+};
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+
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static void
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static void
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nv84_crypt_isr(struct drm_device *dev)
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nv84_crypt_isr(struct drm_device *dev)
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{
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{
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u32 stat = nv_rd32(dev, 0x102130);
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u32 stat = nv_rd32(dev, 0x102130);
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u32 mthd = nv_rd32(dev, 0x102190);
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u32 mthd = nv_rd32(dev, 0x102190);
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u32 data = nv_rd32(dev, 0x102194);
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u32 data = nv_rd32(dev, 0x102194);
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- u32 inst = nv_rd32(dev, 0x102188) & 0x7fffffff;
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+ u64 inst = (u64)(nv_rd32(dev, 0x102188) & 0x7fffffff) << 12;
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int show = nouveau_ratelimit();
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int show = nouveau_ratelimit();
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+ int chid = nv50_graph_isr_chid(dev, inst);
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if (show) {
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if (show) {
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- NV_INFO(dev, "PCRYPT_INTR: 0x%08x 0x%08x 0x%08x 0x%08x\n",
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- stat, mthd, data, inst);
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+ NV_INFO(dev, "PCRYPT:");
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+ nouveau_bitfield_print(nv84_crypt_intr, stat);
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+ printk(KERN_CONT " ch %d (0x%010llx) mthd 0x%04x data 0x%08x\n",
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+ chid, inst, mthd, data);
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}
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}
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nv_wr32(dev, 0x102130, stat);
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nv_wr32(dev, 0x102130, stat);
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Marcin Slusarz