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@@ -202,16 +202,45 @@ nouveau_fifo_irq_handler(struct drm_device *dev)
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}
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}
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if (status & NV_PFIFO_INTR_DMA_PUSHER) {
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if (status & NV_PFIFO_INTR_DMA_PUSHER) {
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- NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d\n", chid);
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+ u32 get = nv_rd32(dev, 0x003244);
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+ u32 put = nv_rd32(dev, 0x003240);
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+ u32 push = nv_rd32(dev, 0x003220);
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+ u32 state = nv_rd32(dev, 0x003228);
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+
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+ if (dev_priv->card_type == NV_50) {
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+ u32 ho_get = nv_rd32(dev, 0x003328);
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+ u32 ho_put = nv_rd32(dev, 0x003320);
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+ u32 ib_get = nv_rd32(dev, 0x003334);
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+ u32 ib_put = nv_rd32(dev, 0x003330);
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+
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+ NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%02x%08x "
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+ "Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x "
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+ "State 0x%08x Push 0x%08x\n",
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+ chid, ho_get, get, ho_put, put, ib_get, ib_put,
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+ state, push);
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+
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+ /* METHOD_COUNT, in DMA_STATE on earlier chipsets */
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+ nv_wr32(dev, 0x003364, 0x00000000);
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+ if (get != put || ho_get != ho_put) {
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+ nv_wr32(dev, 0x003244, put);
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+ nv_wr32(dev, 0x003328, ho_put);
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+ } else
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+ if (ib_get != ib_put) {
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+ nv_wr32(dev, 0x003334, ib_put);
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+ }
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+ } else {
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+ NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%08x "
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+ "Put 0x%08x State 0x%08x Push 0x%08x\n",
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+ chid, get, put, state, push);
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- status &= ~NV_PFIFO_INTR_DMA_PUSHER;
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- nv_wr32(dev, NV03_PFIFO_INTR_0,
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- NV_PFIFO_INTR_DMA_PUSHER);
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+ if (get != put)
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+ nv_wr32(dev, 0x003244, put);
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+ }
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- nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
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- if (nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT) != get)
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- nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET,
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- get + 4);
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+ nv_wr32(dev, 0x003228, 0x00000000);
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+ nv_wr32(dev, 0x003220, 0x00000001);
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+ nv_wr32(dev, 0x002100, NV_PFIFO_INTR_DMA_PUSHER);
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+ status &= ~NV_PFIFO_INTR_DMA_PUSHER;
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}
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}
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if (status & NV_PFIFO_INTR_SEMAPHORE) {
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if (status & NV_PFIFO_INTR_SEMAPHORE) {
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