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@@ -242,25 +242,16 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
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: "m" (rw->lock)
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: "memory");
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} else {
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- __asm__ __volatile__(
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- " .set noreorder # arch_read_lock \n"
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- "1: ll %1, %2 \n"
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- " bltz %1, 3f \n"
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- " addu %1, 1 \n"
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- "2: sc %1, %0 \n"
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- " beqz %1, 1b \n"
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- " nop \n"
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- " .subsection 2 \n"
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- "3: ll %1, %2 \n"
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- " bltz %1, 3b \n"
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- " addu %1, 1 \n"
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- " b 2b \n"
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- " nop \n"
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- " .previous \n"
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- " .set reorder \n"
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- : "=m" (rw->lock), "=&r" (tmp)
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- : "m" (rw->lock)
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- : "memory");
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+ do {
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+ __asm__ __volatile__(
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+ "1: ll %1, %2 # arch_read_lock \n"
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+ " bltz %1, 1b \n"
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+ " addu %1, 1 \n"
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+ "2: sc %1, %0 \n"
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+ : "=m" (rw->lock), "=&r" (tmp)
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+ : "m" (rw->lock)
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+ : "memory");
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+ } while (unlikely(!tmp));
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}
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smp_llsc_mb();
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@@ -285,21 +276,15 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
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: "m" (rw->lock)
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: "memory");
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} else {
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- __asm__ __volatile__(
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- " .set noreorder # arch_read_unlock \n"
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- "1: ll %1, %2 \n"
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- " sub %1, 1 \n"
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- " sc %1, %0 \n"
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- " beqz %1, 2f \n"
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- " nop \n"
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- " .subsection 2 \n"
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- "2: b 1b \n"
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- " nop \n"
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- " .previous \n"
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- " .set reorder \n"
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- : "=m" (rw->lock), "=&r" (tmp)
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- : "m" (rw->lock)
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- : "memory");
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+ do {
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+ __asm__ __volatile__(
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+ "1: ll %1, %2 # arch_read_unlock \n"
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+ " sub %1, 1 \n"
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+ " sc %1, %0 \n"
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+ : "=m" (rw->lock), "=&r" (tmp)
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+ : "m" (rw->lock)
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+ : "memory");
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+ } while (unlikely(!tmp));
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}
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}
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@@ -321,25 +306,16 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
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: "m" (rw->lock)
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: "memory");
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} else {
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- __asm__ __volatile__(
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- " .set noreorder # arch_write_lock \n"
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- "1: ll %1, %2 \n"
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- " bnez %1, 3f \n"
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- " lui %1, 0x8000 \n"
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- "2: sc %1, %0 \n"
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- " beqz %1, 3f \n"
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- " nop \n"
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- " .subsection 2 \n"
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- "3: ll %1, %2 \n"
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- " bnez %1, 3b \n"
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- " lui %1, 0x8000 \n"
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- " b 2b \n"
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- " nop \n"
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- " .previous \n"
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- " .set reorder \n"
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- : "=m" (rw->lock), "=&r" (tmp)
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- : "m" (rw->lock)
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- : "memory");
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+ do {
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+ __asm__ __volatile__(
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+ "1: ll %1, %2 # arch_write_lock \n"
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+ " bnez %1, 1b \n"
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+ " lui %1, 0x8000 \n"
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+ "2: sc %1, %0 \n"
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+ : "=m" (rw->lock), "=&r" (tmp)
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+ : "m" (rw->lock)
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+ : "memory");
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+ } while (unlikely(!tmp));
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}
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smp_llsc_mb();
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@@ -424,25 +400,21 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
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: "m" (rw->lock)
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: "memory");
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} else {
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- __asm__ __volatile__(
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- " .set noreorder # arch_write_trylock \n"
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- " li %2, 0 \n"
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- "1: ll %1, %3 \n"
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- " bnez %1, 2f \n"
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- " lui %1, 0x8000 \n"
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- " sc %1, %0 \n"
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- " beqz %1, 3f \n"
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- " li %2, 1 \n"
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- "2: \n"
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- __WEAK_LLSC_MB
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- " .subsection 2 \n"
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- "3: b 1b \n"
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- " li %2, 0 \n"
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- " .previous \n"
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- " .set reorder \n"
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- : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
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- : "m" (rw->lock)
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- : "memory");
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+ do {
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+ __asm__ __volatile__(
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+ " ll %1, %3 # arch_write_trylock \n"
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+ " li %2, 0 \n"
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+ " bnez %1, 2f \n"
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+ " lui %1, 0x8000 \n"
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+ " sc %1, %0 \n"
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+ " li %2, 1 \n"
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+ "2: \n"
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+ : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
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+ : "m" (rw->lock)
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+ : "memory");
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+ } while (unlikely(!tmp));
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+
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+ smp_llsc_mb();
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}
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return ret;
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