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@@ -1,9 +1,10 @@
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/*
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- * MPC8272_ads setup and early boot code plus other random bits.
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+ * MPC8272 ADS board support
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*
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- * Author: Vitaly Bordug <vbordug@ru.mvista.com>
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- * m82xx_restart fix by Wade Farnsworth <wfarnsworth@mvista.com>
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+ * Copyright 2007 Freescale Semiconductor, Inc.
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+ * Author: Scott Wood <scottwood@freescale.com>
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*
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+ * Based on code by Vitaly Bordug <vbordug@ru.mvista.com>
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* Copyright (c) 2006 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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@@ -12,613 +13,184 @@
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* option) any later version.
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*/
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-#include <linux/stddef.h>
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-#include <linux/kernel.h>
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#include <linux/init.h>
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-#include <linux/errno.h>
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-#include <linux/reboot.h>
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-#include <linux/pci.h>
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#include <linux/interrupt.h>
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-#include <linux/kdev_t.h>
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-#include <linux/major.h>
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-#include <linux/console.h>
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-#include <linux/delay.h>
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-#include <linux/seq_file.h>
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-#include <linux/root_dev.h>
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-#include <linux/initrd.h>
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-#include <linux/module.h>
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#include <linux/fsl_devices.h>
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-#include <linux/fs_uart_pd.h>
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+#include <linux/of_platform.h>
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+#include <linux/io.h>
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-#include <asm/system.h>
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-#include <asm/pgtable.h>
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-#include <asm/page.h>
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-#include <asm/atomic.h>
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-#include <asm/time.h>
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-#include <asm/io.h>
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-#include <asm/machdep.h>
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-#include <asm/pci-bridge.h>
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-#include <asm/mpc8260.h>
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-#include <asm/irq.h>
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-#include <mm/mmu_decl.h>
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-#include <asm/prom.h>
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#include <asm/cpm2.h>
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#include <asm/udbg.h>
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-#include <asm/i8259.h>
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-#include <linux/fs_enet_pd.h>
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+#include <asm/machdep.h>
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+#include <asm/time.h>
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+
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+#include <platforms/82xx/pq2.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/cpm2_pic.h>
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#include "pq2ads.h"
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-
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-#ifdef CONFIG_PCI
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-static uint pci_clk_frq;
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-static struct {
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- unsigned long *pci_int_stat_reg;
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- unsigned long *pci_int_mask_reg;
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-} pci_regs;
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-
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-static unsigned long pci_int_base;
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-static struct irq_host *pci_pic_host;
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-#endif
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+#include "pq2.h"
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static void __init mpc8272_ads_pic_init(void)
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{
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- struct device_node *np = of_find_compatible_node(NULL, "cpm-pic", "CPM2");
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- struct resource r;
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- cpm2_map_t *cpm_reg;
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-
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- if (np == NULL) {
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- printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
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- return;
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- }
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- if (of_address_to_resource(np, 0, &r)) {
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- printk(KERN_ERR "PIC init: invalid resource\n");
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- of_node_put(np);
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+ struct device_node *np = of_find_compatible_node(NULL, NULL,
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+ "fsl,cpm2-pic");
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+ if (!np) {
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+ printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
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return;
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}
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+
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cpm2_pic_init(np);
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of_node_put(np);
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- /* Initialize the default interrupt mapping priorities,
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- * in case the boot rom changed something on us.
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- */
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- cpm_reg = (cpm2_map_t *) ioremap(get_immrbase(), sizeof(cpm2_map_t));
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- cpm_reg->im_intctl.ic_siprr = 0x05309770;
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- iounmap(cpm_reg);
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-#ifdef CONFIG_PCI
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/* Initialize stuff for the 82xx CPLD IC and install demux */
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- m82xx_pci_init_irq();
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-#endif
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+ pq2ads_pci_init_irq();
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}
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-static void init_fcc1_ioports(struct fs_platform_info *fpi)
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-{
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- struct io_port *io;
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- u32 tempval;
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- cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
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- struct device_node *np;
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- struct resource r;
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- u32 *bcsr;
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-
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- np = of_find_node_by_type(NULL, "memory");
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- if (!np) {
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- printk(KERN_INFO "No memory node in device tree\n");
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- return;
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- }
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- if (of_address_to_resource(np, 1, &r)) {
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- printk(KERN_INFO "No memory reg property [1] in devicetree\n");
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- return;
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- }
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- of_node_put(np);
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- bcsr = ioremap(r.start + 4, sizeof(u32));
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- io = &immap->im_ioport;
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-
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- /* Enable the PHY */
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- clrbits32(bcsr, BCSR1_FETHIEN);
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- setbits32(bcsr, BCSR1_FETH_RST);
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-
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- /* FCC1 pins are on port A/C. */
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- /* Configure port A and C pins for FCC1 Ethernet. */
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-
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- tempval = in_be32(&io->iop_pdira);
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- tempval &= ~PA1_DIRA0;
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- tempval |= PA1_DIRA1;
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- out_be32(&io->iop_pdira, tempval);
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-
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- tempval = in_be32(&io->iop_psora);
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- tempval &= ~PA1_PSORA0;
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- tempval |= PA1_PSORA1;
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- out_be32(&io->iop_psora, tempval);
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-
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- setbits32(&io->iop_ppara, PA1_DIRA0 | PA1_DIRA1);
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-
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- /* Alter clocks */
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- tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
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-
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- clrbits32(&io->iop_psorc, tempval);
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- clrbits32(&io->iop_pdirc, tempval);
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- setbits32(&io->iop_pparc, tempval);
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-
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- cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_rx, CPM_CLK_RX);
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- cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_tx, CPM_CLK_TX);
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+struct cpm_pin {
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+ int port, pin, flags;
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+};
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- iounmap(bcsr);
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- iounmap(immap);
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-}
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+static struct cpm_pin mpc8272_ads_pins[] = {
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+ /* SCC1 */
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+ {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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+ {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+
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+ /* SCC4 */
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+ {3, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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+ {3, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+
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+ /* FCC1 */
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+ {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+ {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+ {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+ {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+ {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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+ {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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+ {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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+ {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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+ {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
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+ {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
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+ {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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+ {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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+ {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
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+ {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
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+ {2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+ {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+
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+ /* FCC2 */
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+ {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+ {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+ {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+ {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+ {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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+ {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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+ {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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+ {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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+ {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+ {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+ {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+ {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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+ {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+ {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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+ {2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+ {2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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+};
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-static void init_fcc2_ioports(struct fs_platform_info *fpi)
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+static void __init init_ioports(void)
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{
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- cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
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- struct device_node *np;
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- struct resource r;
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- u32 *bcsr;
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-
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- struct io_port *io;
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- u32 tempval;
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-
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- np = of_find_node_by_type(NULL, "memory");
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- if (!np) {
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- printk(KERN_INFO "No memory node in device tree\n");
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- return;
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- }
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- if (of_address_to_resource(np, 1, &r)) {
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- printk(KERN_INFO "No memory reg property [1] in devicetree\n");
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- return;
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- }
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- of_node_put(np);
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- io = &immap->im_ioport;
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- bcsr = ioremap(r.start + 12, sizeof(u32));
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-
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- /* Enable the PHY */
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- clrbits32(bcsr, BCSR3_FETHIEN2);
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- setbits32(bcsr, BCSR3_FETH2_RST);
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-
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- /* FCC2 are port B/C. */
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- /* Configure port A and C pins for FCC2 Ethernet. */
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-
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- tempval = in_be32(&io->iop_pdirb);
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- tempval &= ~PB2_DIRB0;
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- tempval |= PB2_DIRB1;
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- out_be32(&io->iop_pdirb, tempval);
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-
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- tempval = in_be32(&io->iop_psorb);
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- tempval &= ~PB2_PSORB0;
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- tempval |= PB2_PSORB1;
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- out_be32(&io->iop_psorb, tempval);
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-
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- setbits32(&io->iop_pparb, PB2_DIRB0 | PB2_DIRB1);
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-
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- tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
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-
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- /* Alter clocks */
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- clrbits32(&io->iop_psorc, tempval);
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- clrbits32(&io->iop_pdirc, tempval);
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- setbits32(&io->iop_pparc, tempval);
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-
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- cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_rx, CPM_CLK_RX);
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- cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_tx, CPM_CLK_TX);
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-
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- iounmap(bcsr);
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- iounmap(immap);
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-}
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+ int i;
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-void init_fcc_ioports(struct fs_platform_info *fpi)
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-{
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- int fcc_no = fs_get_fcc_index(fpi->fs_no);
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-
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- switch (fcc_no) {
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- case 0:
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- init_fcc1_ioports(fpi);
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- break;
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- case 1:
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- init_fcc2_ioports(fpi);
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- break;
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- default:
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- printk(KERN_ERR "init_fcc_ioports: invalid FCC number\n");
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- return;
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+ for (i = 0; i < ARRAY_SIZE(mpc8272_ads_pins); i++) {
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+ struct cpm_pin *pin = &mpc8272_ads_pins[i];
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+ cpm2_set_pin(pin->port, pin->pin, pin->flags);
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}
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-}
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-static void init_scc1_uart_ioports(struct fs_uart_platform_info *data)
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-{
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- cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
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-
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- /* SCC1 is only on port D */
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- setbits32(&immap->im_ioport.iop_ppard, 0x00000003);
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- clrbits32(&immap->im_ioport.iop_psord, 0x00000001);
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- setbits32(&immap->im_ioport.iop_psord, 0x00000002);
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- clrbits32(&immap->im_ioport.iop_pdird, 0x00000001);
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- setbits32(&immap->im_ioport.iop_pdird, 0x00000002);
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-
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- clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
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- clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
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- setbits32(&immap->im_cpmux.cmx_scr,
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- ((data->clk_tx - 1) << (4 - data->clk_tx)));
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- setbits32(&immap->im_cpmux.cmx_scr,
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- ((data->clk_rx - 1) << (4 - data->clk_rx)));
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-
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- iounmap(immap);
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+ cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
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+ cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
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+ cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_RX);
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+ cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_TX);
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+ cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX);
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+ cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX);
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+ cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK15, CPM_CLK_RX);
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+ cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK16, CPM_CLK_TX);
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}
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-static void init_scc4_uart_ioports(struct fs_uart_platform_info *data)
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+static void __init mpc8272_ads_setup_arch(void)
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{
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- cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
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-
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- setbits32(&immap->im_ioport.iop_ppard, 0x00000600);
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- clrbits32(&immap->im_ioport.iop_psord, 0x00000600);
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- clrbits32(&immap->im_ioport.iop_pdird, 0x00000200);
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- setbits32(&immap->im_ioport.iop_pdird, 0x00000400);
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-
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- clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
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- clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
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- setbits32(&immap->im_cpmux.cmx_scr,
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- ((data->clk_tx - 1) << (4 - data->clk_tx)));
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- setbits32(&immap->im_cpmux.cmx_scr,
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- ((data->clk_rx - 1) << (4 - data->clk_rx)));
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-
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- iounmap(immap);
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-}
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+ struct device_node *np;
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+ __be32 __iomem *bcsr;
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-void init_scc_ioports(struct fs_uart_platform_info *data)
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-{
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- int scc_no = fs_get_scc_index(data->fs_no);
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-
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|
|
- switch (scc_no) {
|
|
|
- case 0:
|
|
|
- init_scc1_uart_ioports(data);
|
|
|
- data->brg = data->clk_rx;
|
|
|
- break;
|
|
|
- case 3:
|
|
|
- init_scc4_uart_ioports(data);
|
|
|
- data->brg = data->clk_rx;
|
|
|
- break;
|
|
|
- default:
|
|
|
- printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
|
|
|
- return;
|
|
|
- }
|
|
|
-}
|
|
|
+ if (ppc_md.progress)
|
|
|
+ ppc_md.progress("mpc8272_ads_setup_arch()", 0);
|
|
|
|
|
|
-void __init m82xx_board_setup(void)
|
|
|
-{
|
|
|
- cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
|
|
|
- struct device_node *np;
|
|
|
- struct resource r;
|
|
|
- u32 *bcsr;
|
|
|
+ cpm2_reset();
|
|
|
|
|
|
- np = of_find_node_by_type(NULL, "memory");
|
|
|
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc8272ads-bcsr");
|
|
|
if (!np) {
|
|
|
- printk(KERN_INFO "No memory node in device tree\n");
|
|
|
+ printk(KERN_ERR "No bcsr in device tree\n");
|
|
|
return;
|
|
|
}
|
|
|
- if (of_address_to_resource(np, 1, &r)) {
|
|
|
- printk(KERN_INFO "No memory reg property [1] in devicetree\n");
|
|
|
+
|
|
|
+ bcsr = of_iomap(np, 0);
|
|
|
+ if (!bcsr) {
|
|
|
+ printk(KERN_ERR "Cannot map BCSR registers\n");
|
|
|
return;
|
|
|
}
|
|
|
- of_node_put(np);
|
|
|
- bcsr = ioremap(r.start + 4, sizeof(u32));
|
|
|
- /* Enable the 2nd UART port */
|
|
|
- clrbits32(bcsr, BCSR1_RS232_EN2);
|
|
|
-
|
|
|
-#ifdef CONFIG_SERIAL_CPM_SCC1
|
|
|
- clrbits32((u32 *) & immap->im_scc[0].scc_sccm,
|
|
|
- UART_SCCM_TX | UART_SCCM_RX);
|
|
|
- clrbits32((u32 *) & immap->im_scc[0].scc_gsmrl,
|
|
|
- SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
|
|
-#endif
|
|
|
-
|
|
|
-#ifdef CONFIG_SERIAL_CPM_SCC2
|
|
|
- clrbits32((u32 *) & immap->im_scc[1].scc_sccm,
|
|
|
- UART_SCCM_TX | UART_SCCM_RX);
|
|
|
- clrbits32((u32 *) & immap->im_scc[1].scc_gsmrl,
|
|
|
- SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
|
|
-#endif
|
|
|
-
|
|
|
-#ifdef CONFIG_SERIAL_CPM_SCC3
|
|
|
- clrbits32((u32 *) & immap->im_scc[2].scc_sccm,
|
|
|
- UART_SCCM_TX | UART_SCCM_RX);
|
|
|
- clrbits32((u32 *) & immap->im_scc[2].scc_gsmrl,
|
|
|
- SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
|
|
-#endif
|
|
|
-
|
|
|
-#ifdef CONFIG_SERIAL_CPM_SCC4
|
|
|
- clrbits32((u32 *) & immap->im_scc[3].scc_sccm,
|
|
|
- UART_SCCM_TX | UART_SCCM_RX);
|
|
|
- clrbits32((u32 *) & immap->im_scc[3].scc_gsmrl,
|
|
|
- SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
|
|
-#endif
|
|
|
-
|
|
|
- iounmap(bcsr);
|
|
|
- iounmap(immap);
|
|
|
-}
|
|
|
-
|
|
|
-#ifdef CONFIG_PCI
|
|
|
-static void m82xx_pci_mask_irq(unsigned int irq)
|
|
|
-{
|
|
|
- int bit = irq - pci_int_base;
|
|
|
|
|
|
- *pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
|
|
|
- return;
|
|
|
-}
|
|
|
+ of_node_put(np);
|
|
|
|
|
|
-static void m82xx_pci_unmask_irq(unsigned int irq)
|
|
|
-{
|
|
|
- int bit = irq - pci_int_base;
|
|
|
+ clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
|
|
|
+ setbits32(&bcsr[1], BCSR1_FETH_RST);
|
|
|
|
|
|
- *pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
|
|
|
- return;
|
|
|
-}
|
|
|
+ clrbits32(&bcsr[3], BCSR3_FETHIEN2);
|
|
|
+ setbits32(&bcsr[3], BCSR3_FETH2_RST);
|
|
|
|
|
|
-static void m82xx_pci_mask_and_ack(unsigned int irq)
|
|
|
-{
|
|
|
- int bit = irq - pci_int_base;
|
|
|
-
|
|
|
- *pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
|
|
|
- return;
|
|
|
-}
|
|
|
+ iounmap(bcsr);
|
|
|
|
|
|
-static void m82xx_pci_end_irq(unsigned int irq)
|
|
|
-{
|
|
|
- int bit = irq - pci_int_base;
|
|
|
+ init_ioports();
|
|
|
+ pq2_init_pci();
|
|
|
|
|
|
- *pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
|
|
|
- return;
|
|
|
+ if (ppc_md.progress)
|
|
|
+ ppc_md.progress("mpc8272_ads_setup_arch(), finish", 0);
|
|
|
}
|
|
|
|
|
|
-struct hw_interrupt_type m82xx_pci_ic = {
|
|
|
- .typename = "MPC82xx ADS PCI",
|
|
|
- .name = "MPC82xx ADS PCI",
|
|
|
- .enable = m82xx_pci_unmask_irq,
|
|
|
- .disable = m82xx_pci_mask_irq,
|
|
|
- .ack = m82xx_pci_mask_and_ack,
|
|
|
- .end = m82xx_pci_end_irq,
|
|
|
- .mask = m82xx_pci_mask_irq,
|
|
|
- .mask_ack = m82xx_pci_mask_and_ack,
|
|
|
- .unmask = m82xx_pci_unmask_irq,
|
|
|
- .eoi = m82xx_pci_end_irq,
|
|
|
+static struct of_device_id __initdata of_bus_ids[] = {
|
|
|
+ { .name = "soc", },
|
|
|
+ { .name = "cpm", },
|
|
|
+ { .name = "localbus", },
|
|
|
+ {},
|
|
|
};
|
|
|
|
|
|
-static void
|
|
|
-m82xx_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
|
|
|
+static int __init declare_of_platform_devices(void)
|
|
|
{
|
|
|
- unsigned long stat, mask, pend;
|
|
|
- int bit;
|
|
|
-
|
|
|
- for (;;) {
|
|
|
- stat = *pci_regs.pci_int_stat_reg;
|
|
|
- mask = *pci_regs.pci_int_mask_reg;
|
|
|
- pend = stat & ~mask & 0xf0000000;
|
|
|
- if (!pend)
|
|
|
- break;
|
|
|
- for (bit = 0; pend != 0; ++bit, pend <<= 1) {
|
|
|
- if (pend & 0x80000000)
|
|
|
- __do_IRQ(pci_int_base + bit);
|
|
|
- }
|
|
|
- }
|
|
|
-}
|
|
|
+ if (!machine_is(mpc8272_ads))
|
|
|
+ return 0;
|
|
|
|
|
|
-static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
|
|
|
- irq_hw_number_t hw)
|
|
|
-{
|
|
|
- get_irq_desc(virq)->status |= IRQ_LEVEL;
|
|
|
- set_irq_chip(virq, &m82xx_pci_ic);
|
|
|
+ /* Publish the QE devices */
|
|
|
+ of_platform_bus_probe(NULL, of_bus_ids, NULL);
|
|
|
return 0;
|
|
|
}
|
|
|
-
|
|
|
-static void pci_host_unmap(struct irq_host *h, unsigned int virq)
|
|
|
-{
|
|
|
- /* remove chip and handler */
|
|
|
- set_irq_chip(virq, NULL);
|
|
|
-}
|
|
|
-
|
|
|
-static struct irq_host_ops pci_pic_host_ops = {
|
|
|
- .map = pci_pic_host_map,
|
|
|
- .unmap = pci_host_unmap,
|
|
|
-};
|
|
|
-
|
|
|
-void m82xx_pci_init_irq(void)
|
|
|
-{
|
|
|
- int irq;
|
|
|
- cpm2_map_t *immap;
|
|
|
- struct device_node *np;
|
|
|
- struct resource r;
|
|
|
- const u32 *regs;
|
|
|
- unsigned int size;
|
|
|
- const u32 *irq_map;
|
|
|
- int i;
|
|
|
- unsigned int irq_max, irq_min;
|
|
|
-
|
|
|
- if ((np = of_find_node_by_type(NULL, "soc")) == NULL) {
|
|
|
- printk(KERN_INFO "No SOC node in device tree\n");
|
|
|
- return;
|
|
|
- }
|
|
|
- memset(&r, 0, sizeof(r));
|
|
|
- if (of_address_to_resource(np, 0, &r)) {
|
|
|
- printk(KERN_INFO "No SOC reg property in device tree\n");
|
|
|
- return;
|
|
|
- }
|
|
|
- immap = ioremap(r.start, sizeof(*immap));
|
|
|
- of_node_put(np);
|
|
|
-
|
|
|
- /* install the demultiplexer for the PCI cascade interrupt */
|
|
|
- np = of_find_node_by_type(NULL, "pci");
|
|
|
- if (!np) {
|
|
|
- printk(KERN_INFO "No pci node on device tree\n");
|
|
|
- iounmap(immap);
|
|
|
- return;
|
|
|
- }
|
|
|
- irq_map = of_get_property(np, "interrupt-map", &size);
|
|
|
- if ((!irq_map) || (size <= 7)) {
|
|
|
- printk(KERN_INFO "No interrupt-map property of pci node\n");
|
|
|
- iounmap(immap);
|
|
|
- return;
|
|
|
- }
|
|
|
- size /= sizeof(irq_map[0]);
|
|
|
- for (i = 0, irq_max = 0, irq_min = 512; i < size; i += 7, irq_map += 7) {
|
|
|
- if (irq_map[5] < irq_min)
|
|
|
- irq_min = irq_map[5];
|
|
|
- if (irq_map[5] > irq_max)
|
|
|
- irq_max = irq_map[5];
|
|
|
- }
|
|
|
- pci_int_base = irq_min;
|
|
|
- irq = irq_of_parse_and_map(np, 0);
|
|
|
- set_irq_chained_handler(irq, m82xx_pci_irq_demux);
|
|
|
- of_node_put(np);
|
|
|
- np = of_find_node_by_type(NULL, "pci-pic");
|
|
|
- if (!np) {
|
|
|
- printk(KERN_INFO "No pci pic node on device tree\n");
|
|
|
- iounmap(immap);
|
|
|
- return;
|
|
|
- }
|
|
|
- /* PCI interrupt controller registers: status and mask */
|
|
|
- regs = of_get_property(np, "reg", &size);
|
|
|
- if ((!regs) || (size <= 2)) {
|
|
|
- printk(KERN_INFO "No reg property in pci pic node\n");
|
|
|
- iounmap(immap);
|
|
|
- return;
|
|
|
- }
|
|
|
- pci_regs.pci_int_stat_reg =
|
|
|
- ioremap(regs[0], sizeof(*pci_regs.pci_int_stat_reg));
|
|
|
- pci_regs.pci_int_mask_reg =
|
|
|
- ioremap(regs[1], sizeof(*pci_regs.pci_int_mask_reg));
|
|
|
- /* configure chip select for PCI interrupt controller */
|
|
|
- immap->im_memctl.memc_br3 = regs[0] | 0x00001801;
|
|
|
- immap->im_memctl.memc_or3 = 0xffff8010;
|
|
|
- /* make PCI IRQ level sensitive */
|
|
|
- immap->im_intctl.ic_siexr &= ~(1 << (14 - (irq - SIU_INT_IRQ1)));
|
|
|
-
|
|
|
- /* mask all PCI interrupts */
|
|
|
- *pci_regs.pci_int_mask_reg |= 0xfff00000;
|
|
|
- iounmap(immap);
|
|
|
- pci_pic_host =
|
|
|
- irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, irq_max - irq_min + 1,
|
|
|
- &pci_pic_host_ops, irq_max + 1);
|
|
|
- return;
|
|
|
-}
|
|
|
-
|
|
|
-static int m82xx_pci_exclude_device(struct pci_controller *hose,
|
|
|
- u_char bus, u_char devfn)
|
|
|
-{
|
|
|
- if (bus == 0 && PCI_SLOT(devfn) == 0)
|
|
|
- return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
- else
|
|
|
- return PCIBIOS_SUCCESSFUL;
|
|
|
-}
|
|
|
-
|
|
|
-static void __init mpc82xx_add_bridge(struct device_node *np)
|
|
|
-{
|
|
|
- int len;
|
|
|
- struct pci_controller *hose;
|
|
|
- struct resource r;
|
|
|
- const int *bus_range;
|
|
|
- const uint *ptr;
|
|
|
-
|
|
|
- memset(&r, 0, sizeof(r));
|
|
|
- if (of_address_to_resource(np, 0, &r)) {
|
|
|
- printk(KERN_INFO "No PCI reg property in device tree\n");
|
|
|
- return;
|
|
|
- }
|
|
|
- if (!(ptr = of_get_property(np, "clock-frequency", NULL))) {
|
|
|
- printk(KERN_INFO "No clock-frequency property in PCI node");
|
|
|
- return;
|
|
|
- }
|
|
|
- pci_clk_frq = *ptr;
|
|
|
- of_node_put(np);
|
|
|
- bus_range = of_get_property(np, "bus-range", &len);
|
|
|
- if (bus_range == NULL || len < 2 * sizeof(int)) {
|
|
|
- printk(KERN_WARNING "Can't get bus-range for %s, assume"
|
|
|
- " bus 0\n", np->full_name);
|
|
|
- }
|
|
|
-
|
|
|
- pci_assign_all_buses = 1;
|
|
|
-
|
|
|
- hose = pcibios_alloc_controller(np);
|
|
|
-
|
|
|
- if (!hose)
|
|
|
- return;
|
|
|
-
|
|
|
- hose->first_busno = bus_range ? bus_range[0] : 0;
|
|
|
- hose->last_busno = bus_range ? bus_range[1] : 0xff;
|
|
|
-
|
|
|
- setup_indirect_pci(hose,
|
|
|
- r.start + offsetof(pci_cpm2_t, pci_cfg_addr),
|
|
|
- r.start + offsetof(pci_cpm2_t, pci_cfg_data),
|
|
|
- 0);
|
|
|
-
|
|
|
- pci_process_bridge_OF_ranges(hose, np, 1);
|
|
|
-}
|
|
|
-#endif
|
|
|
-
|
|
|
-/*
|
|
|
- * Setup the architecture
|
|
|
- */
|
|
|
-static void __init mpc8272_ads_setup_arch(void)
|
|
|
-{
|
|
|
-#ifdef CONFIG_PCI
|
|
|
- struct device_node *np;
|
|
|
-#endif
|
|
|
-
|
|
|
- if (ppc_md.progress)
|
|
|
- ppc_md.progress("mpc8272_ads_setup_arch()", 0);
|
|
|
- cpm2_reset();
|
|
|
-
|
|
|
- /* Map I/O region to a 256MB BAT */
|
|
|
-
|
|
|
- m82xx_board_setup();
|
|
|
-
|
|
|
-#ifdef CONFIG_PCI
|
|
|
- ppc_md.pci_exclude_device = m82xx_pci_exclude_device;
|
|
|
- for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
|
|
|
- mpc82xx_add_bridge(np);
|
|
|
-
|
|
|
- of_node_put(np);
|
|
|
-#endif
|
|
|
-
|
|
|
-#ifdef CONFIG_ROOT_NFS
|
|
|
- ROOT_DEV = Root_NFS;
|
|
|
-#else
|
|
|
- ROOT_DEV = Root_HDA1;
|
|
|
-#endif
|
|
|
-
|
|
|
- if (ppc_md.progress)
|
|
|
- ppc_md.progress("mpc8272_ads_setup_arch(), finish", 0);
|
|
|
-}
|
|
|
+device_initcall(declare_of_platform_devices);
|
|
|
|
|
|
/*
|
|
|
* Called very early, device-tree isn't unflattened
|
|
|
*/
|
|
|
static int __init mpc8272_ads_probe(void)
|
|
|
{
|
|
|
- /* We always match for now, eventually we should look at
|
|
|
- * the flat dev tree to ensure this is the board we are
|
|
|
- * supposed to run on
|
|
|
- */
|
|
|
- return 1;
|
|
|
-}
|
|
|
-
|
|
|
-#define RMR_CSRE 0x00000001
|
|
|
-static void m82xx_restart(char *cmd)
|
|
|
-{
|
|
|
- __volatile__ unsigned char dummy;
|
|
|
-
|
|
|
- local_irq_disable();
|
|
|
- ((cpm2_map_t *) cpm2_immr)->im_clkrst.car_rmr |= RMR_CSRE;
|
|
|
-
|
|
|
- /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
|
|
|
- mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
|
|
|
- dummy = ((cpm2_map_t *) cpm2_immr)->im_clkrst.res[0];
|
|
|
- printk("Restart failed\n");
|
|
|
- while (1) ;
|
|
|
+ unsigned long root = of_get_flat_dt_root();
|
|
|
+ return of_flat_dt_is_compatible(root, "fsl,mpc8272ads");
|
|
|
}
|
|
|
|
|
|
define_machine(mpc8272_ads)
|
|
|
{
|
|
|
- .name = "MPC8272 ADS",
|
|
|
- .probe = mpc8272_ads_probe,
|
|
|
- .setup_arch = mpc8272_ads_setup_arch,
|
|
|
- .init_IRQ = mpc8272_ads_pic_init,
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- .get_irq = cpm2_get_irq,
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+ .name = "Freescale MPC8272 ADS",
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+ .probe = mpc8272_ads_probe,
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+ .setup_arch = mpc8272_ads_setup_arch,
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+ .init_IRQ = mpc8272_ads_pic_init,
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+ .get_irq = cpm2_get_irq,
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.calibrate_decr = generic_calibrate_decr,
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- .restart = m82xx_restart,
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+ .restart = pq2_restart,
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+ .progress = udbg_progress,
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};
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Scott Wood