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@@ -967,7 +967,7 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
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struct ath9k_hw_cal_data *caldata = ah->caldata;
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bool txiqcal_done = false, txclcal_done = false;
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bool is_reusable = true, status = true;
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- bool run_rtt_cal = false, run_agc_cal;
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+ bool run_rtt_cal = false, run_agc_cal, sep_iq_cal = false;
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bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
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u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
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AR_PHY_AGC_CONTROL_FLTR_CAL |
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@@ -1034,19 +1034,22 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
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REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
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AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
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txiqcal_done = run_agc_cal = true;
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- goto skip_tx_iqcal;
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- } else if (caldata && !caldata->done_txiqcal_once)
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+ } else if (caldata && !caldata->done_txiqcal_once) {
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run_agc_cal = true;
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+ sep_iq_cal = true;
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+ }
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+skip_tx_iqcal:
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if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
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ar9003_mci_init_cal_req(ah, &is_reusable);
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- txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
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- REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
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- udelay(5);
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- REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
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+ if (sep_iq_cal) {
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+ txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
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+ REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
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+ udelay(5);
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+ REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
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+ }
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-skip_tx_iqcal:
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if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
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/* Calibrate the AGC */
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REG_WRITE(ah, AR_PHY_AGC_CONTROL,
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