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@@ -98,7 +98,7 @@ static struct init_tab {
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{ 0xac, 0x1003, },
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{ 0xad, 0x103f, },
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{ 0xe2, 0x0100, },
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- { 0xe3, 0x0000, },
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+ { 0xe3, 0x1000, },
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{ 0x28, 0x1010, },
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{ 0xb1, 0x000e, },
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};
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@@ -441,9 +441,11 @@ static int s5h1409_set_gpio(struct dvb_frontend* fe, int enable)
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dprintk("%s(%d)\n", __FUNCTION__, enable);
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if (enable)
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- return s5h1409_writereg(state, 0xe3, 0x1100);
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+ return s5h1409_writereg(state, 0xe3,
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+ s5h1409_readreg(state, 0xe3) | 0x1100);
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else
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- return s5h1409_writereg(state, 0xe3, 0x1000);
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+ return s5h1409_writereg(state, 0xe3,
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+ s5h1409_readreg(state, 0xe3) & 0xeeff);
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}
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static int s5h1409_sleep(struct dvb_frontend* fe, int enable)
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@@ -513,13 +515,15 @@ static void s5h1409_set_qam_interleave_mode(struct dvb_frontend *fe)
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s5h1409_writereg(state, 0x96, 0x20);
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s5h1409_writereg(state, 0xad,
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( ((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff)) );
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- s5h1409_writereg(state, 0xab, 0x1100);
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+ s5h1409_writereg(state, 0xab,
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+ s5h1409_readreg(state, 0xab) & 0xeffe);
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}
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} else {
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if (state->qam_state != 1) {
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state->qam_state = 1;
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s5h1409_writereg(state, 0x96, 0x08);
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- s5h1409_writereg(state, 0xab, 0x1101);
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+ s5h1409_writereg(state, 0xab,
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+ s5h1409_readreg(state, 0xab) | 0x1001);
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}
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}
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}
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@@ -556,6 +560,36 @@ static int s5h1409_set_frontend (struct dvb_frontend* fe,
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return 0;
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}
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+static int s5h1409_set_mpeg_timing(struct dvb_frontend *fe, int mode)
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+{
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+ struct s5h1409_state *state = fe->demodulator_priv;
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+ u16 val;
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+
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+ dprintk("%s(%d)\n", __FUNCTION__, mode);
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+
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+ val = s5h1409_readreg(state, 0xac) & 0xcfff;
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+ switch (mode) {
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+ case S5H1409_MPEGTIMING_CONTINOUS_INVERTING_CLOCK:
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+ val |= 0x0000;
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+ break;
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+ case S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK:
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+ dprintk("%s(%d) Mode1 or Defaulting\n", __FUNCTION__, mode);
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+ val |= 0x1000;
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+ break;
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+ case S5H1409_MPEGTIMING_NONCONTINOUS_INVERTING_CLOCK:
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+ val |= 0x2000;
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+ break;
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+ case S5H1409_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK:
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+ val |= 0x3000;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ /* Configure MPEG Signal Timing charactistics */
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+ return s5h1409_writereg(state, 0xac, val);
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+}
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+
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/* Reset the demod hardware and reset all of the configuration registers
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to a default state. */
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static int s5h1409_init (struct dvb_frontend* fe)
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@@ -575,13 +609,16 @@ static int s5h1409_init (struct dvb_frontend* fe)
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state->current_modulation = VSB_8;
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if (state->config->output_mode == S5H1409_SERIAL_OUTPUT)
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- s5h1409_writereg(state, 0xab, 0x100); /* Serial */
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+ s5h1409_writereg(state, 0xab,
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+ s5h1409_readreg(state, 0xab) | 0x100); /* Serial */
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else
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- s5h1409_writereg(state, 0xab, 0x0); /* Parallel */
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+ s5h1409_writereg(state, 0xab,
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+ s5h1409_readreg(state, 0xab) & 0xfeff); /* Parallel */
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s5h1409_set_spectralinversion(fe, state->config->inversion);
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s5h1409_set_if_freq(fe, state->if_freq);
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s5h1409_set_gpio(fe, state->config->gpio);
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+ s5h1409_set_mpeg_timing(fe, state->config->mpeg_timing);
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s5h1409_softreset(fe);
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/* Note: Leaving the I2C gate closed. */
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