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@@ -181,7 +181,7 @@ static u32 opcode_table[256] = {
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ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String,
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ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String,
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/* 0xA8 - 0xAF */
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- 0, 0, ByteOp | DstDI | Mov | String, DstDI | Mov | String,
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+ DstAcc | SrcImmByte | ByteOp, DstAcc | SrcImm, ByteOp | DstDI | Mov | String, DstDI | Mov | String,
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ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String,
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ByteOp | DstDI | String, DstDI | String,
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/* 0xB0 - 0xB7 */
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@@ -2754,6 +2754,7 @@ special_insn:
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}
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break;
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case 0x84 ... 0x85:
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+ test:
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emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
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break;
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case 0x86 ... 0x87: /* xchg */
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@@ -2852,6 +2853,8 @@ special_insn:
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c->dst.type = OP_NONE; /* Disable writeback. */
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DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
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goto cmp;
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+ case 0xa8 ... 0xa9: /* test ax, imm */
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+ goto test;
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case 0xaa ... 0xab: /* stos */
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c->dst.val = c->regs[VCPU_REGS_RAX];
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break;
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