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@@ -136,7 +136,7 @@ void si_pmu_set_ldo_voltage(si_t *sih, struct osl_info *osh, u8 ldo, u8 voltage)
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ASSERT(sih->cccaps & CC_CAP_PMU);
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM4336_CHIP_ID:
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switch (ldo) {
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case SET_LDO_VOLTAGE_CLDO_PWM:
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@@ -204,7 +204,7 @@ u16 si_pmu_fast_pwrup_delay(si_t *sih, struct osl_info *osh)
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cc = si_setcoreidx(sih, SI_CC_IDX);
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ASSERT(cc != NULL);
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM43224_CHIP_ID:
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case BCM43225_CHIP_ID:
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case BCM43421_CHIP_ID:
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@@ -604,7 +604,7 @@ static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax)
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rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
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/* determine min/max rsrc masks */
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM43224_CHIP_ID:
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case BCM43225_CHIP_ID:
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case BCM43421_CHIP_ID:
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@@ -701,7 +701,7 @@ void si_pmu_res_init(si_t *sih, struct osl_info *osh)
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cc = si_setcoreidx(sih, SI_CC_IDX);
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ASSERT(cc != NULL);
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM4329_CHIP_ID:
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/* Optimize resources up/down timers */
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if (ISSIM_ENAB(sih)) {
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@@ -1100,7 +1100,7 @@ static const pmu1_xtaltab0_t *si_pmu1_xtaltab0(si_t *sih)
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#ifdef BCMDBG
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char chn[8];
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#endif
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM4329_CHIP_ID:
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return pmu1_xtaltab0_880_4329;
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case BCM4319_CHIP_ID:
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@@ -1128,7 +1128,7 @@ static const pmu1_xtaltab0_t *si_pmu1_xtaldef0(si_t *sih)
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char chn[8];
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#endif
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM4329_CHIP_ID:
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/* Default to 38400Khz */
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return &pmu1_xtaltab0_880_4329[PMU1_XTALTAB0_880_38400K];
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@@ -1160,7 +1160,7 @@ static u32 si_pmu1_pllfvco0(si_t *sih)
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char chn[8];
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#endif
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM4329_CHIP_ID:
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return FVCO_880;
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case BCM4319_CHIP_ID:
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@@ -1239,8 +1239,8 @@ static void si_pmu1_pllinit0(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
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*/
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if ((((R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
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PCTL_XTALFREQ_SHIFT) == xt->xf) &&
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- !((CHIPID(sih->chip) == BCM4319_CHIP_ID)
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- || (CHIPID(sih->chip) == BCM4330_CHIP_ID))) {
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+ !((sih->chip == BCM4319_CHIP_ID)
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+ || (sih->chip == BCM4330_CHIP_ID))) {
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PMU_MSG(("PLL already programmed for %d.%d MHz\n",
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xt->fref / 1000, xt->fref % 1000));
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return;
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@@ -1250,7 +1250,7 @@ static void si_pmu1_pllinit0(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
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PMU_MSG(("Programming PLL for %d.%d MHz\n", xt->fref / 1000,
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xt->fref % 1000));
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM4329_CHIP_ID:
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/* Change the BBPLL drive strength to 8 for all channels */
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buf_strength = 0x888888;
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@@ -1357,10 +1357,10 @@ static void si_pmu1_pllinit0(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
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p2div << PMU1_PLL0_PC0_P2DIV_SHIFT) & PMU1_PLL0_PC0_P2DIV_MASK);
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W_REG(osh, &cc->pllcontrol_data, tmp);
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- if ((CHIPID(sih->chip) == BCM4330_CHIP_ID))
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+ if ((sih->chip == BCM4330_CHIP_ID))
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si_pmu_set_4330_plldivs(sih);
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- if ((CHIPID(sih->chip) == BCM4329_CHIP_ID)
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+ if ((sih->chip == BCM4329_CHIP_ID)
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&& (CHIPREV(sih->chiprev) == 0)) {
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W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
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@@ -1369,9 +1369,9 @@ static void si_pmu1_pllinit0(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
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tmp = tmp | DOT11MAC_880MHZ_CLK_DIVISOR_VAL;
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W_REG(osh, &cc->pllcontrol_data, tmp);
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}
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- if ((CHIPID(sih->chip) == BCM4319_CHIP_ID) ||
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- (CHIPID(sih->chip) == BCM4336_CHIP_ID) ||
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- (CHIPID(sih->chip) == BCM4330_CHIP_ID))
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+ if ((sih->chip == BCM4319_CHIP_ID) ||
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+ (sih->chip == BCM4336_CHIP_ID) ||
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+ (sih->chip == BCM4330_CHIP_ID))
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ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MFB;
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else
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ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MASH;
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@@ -1413,7 +1413,7 @@ static void si_pmu1_pllinit0(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
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/* to operate the 4319 usb in 24MHz/48MHz; chipcontrol[2][84:83] needs
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* to be updated.
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*/
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- if ((CHIPID(sih->chip) == BCM4319_CHIP_ID)
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+ if ((sih->chip == BCM4319_CHIP_ID)
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&& (xt->fref != XTAL_FREQ_30000MHZ)) {
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W_REG(osh, &cc->chipcontrol_addr, PMU1_PLL0_CHIPCTL2);
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tmp =
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@@ -1442,7 +1442,7 @@ static void si_pmu1_pllinit0(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
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PCTL_ILP_DIV_MASK) |
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((xt->xf << PCTL_XTALFREQ_SHIFT) & PCTL_XTALFREQ_MASK);
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- if ((CHIPID(sih->chip) == BCM4329_CHIP_ID)
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+ if ((sih->chip == BCM4329_CHIP_ID)
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&& CHIPREV(sih->chiprev) == 0) {
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/* clear the htstretch before clearing HTReqEn */
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AND_REG(osh, &cc->clkstretch, ~CSTRETCH_HT);
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@@ -1523,7 +1523,7 @@ void si_pmu_pll_init(si_t *sih, struct osl_info *osh, uint xtalfreq)
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cc = si_setcoreidx(sih, SI_CC_IDX);
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ASSERT(cc != NULL);
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM4329_CHIP_ID:
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if (xtalfreq == 0)
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xtalfreq = 38400;
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@@ -1577,7 +1577,7 @@ u32 si_pmu_alp_clock(si_t *sih, struct osl_info *osh)
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cc = si_setcoreidx(sih, SI_CC_IDX);
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ASSERT(cc != NULL);
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM43224_CHIP_ID:
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case BCM43225_CHIP_ID:
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case BCM43421_CHIP_ID:
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@@ -1637,7 +1637,7 @@ si_pmu5_clock(si_t *sih, struct osl_info *osh, chipcregs_t *cc, uint pll0,
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return 0;
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}
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- if (CHIPID(sih->chip) == BCM5357_CHIP_ID) {
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+ if (sih->chip == BCM5357_CHIP_ID) {
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/* Detect failure in clock setting */
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if ((R_REG(osh, &cc->chipstatus) & 0x40000) != 0) {
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return 133 * 1000000;
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@@ -1691,7 +1691,7 @@ u32 si_pmu_si_clock(si_t *sih, struct osl_info *osh)
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cc = si_setcoreidx(sih, SI_CC_IDX);
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ASSERT(cc != NULL);
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM43224_CHIP_ID:
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case BCM43225_CHIP_ID:
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case BCM43421_CHIP_ID:
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@@ -1763,14 +1763,14 @@ u32 si_pmu_cpu_clock(si_t *sih, struct osl_info *osh)
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ASSERT(sih->cccaps & CC_CAP_PMU);
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if ((sih->pmurev >= 5) &&
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- !((CHIPID(sih->chip) == BCM4329_CHIP_ID) ||
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- (CHIPID(sih->chip) == BCM4319_CHIP_ID) ||
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- (CHIPID(sih->chip) == BCM43236_CHIP_ID) ||
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- (CHIPID(sih->chip) == BCM4336_CHIP_ID) ||
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- (CHIPID(sih->chip) == BCM4330_CHIP_ID))) {
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+ !((sih->chip == BCM4329_CHIP_ID) ||
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+ (sih->chip == BCM4319_CHIP_ID) ||
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+ (sih->chip == BCM43236_CHIP_ID) ||
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+ (sih->chip == BCM4336_CHIP_ID) ||
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+ (sih->chip == BCM4330_CHIP_ID))) {
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uint pll;
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM5356_CHIP_ID:
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pll = PMU5356_MAINPLL_PLL0;
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break;
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@@ -1807,14 +1807,14 @@ u32 si_pmu_mem_clock(si_t *sih, struct osl_info *osh)
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ASSERT(sih->cccaps & CC_CAP_PMU);
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if ((sih->pmurev >= 5) &&
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- !((CHIPID(sih->chip) == BCM4329_CHIP_ID) ||
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- (CHIPID(sih->chip) == BCM4319_CHIP_ID) ||
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- (CHIPID(sih->chip) == BCM4330_CHIP_ID) ||
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- (CHIPID(sih->chip) == BCM4336_CHIP_ID) ||
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- (CHIPID(sih->chip) == BCM43236_CHIP_ID))) {
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+ !((sih->chip == BCM4329_CHIP_ID) ||
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+ (sih->chip == BCM4319_CHIP_ID) ||
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+ (sih->chip == BCM4330_CHIP_ID) ||
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+ (sih->chip == BCM4336_CHIP_ID) ||
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+ (sih->chip == BCM43236_CHIP_ID))) {
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uint pll;
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM5356_CHIP_ID:
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pll = PMU5356_MAINPLL_PLL0;
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break;
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@@ -1999,7 +1999,7 @@ void si_pmu_init(si_t *sih, struct osl_info *osh)
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else if (sih->pmurev >= 2)
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OR_REG(osh, &cc->pmucontrol, PCTL_NOILP_ON_WAIT);
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- if ((CHIPID(sih->chip) == BCM4329_CHIP_ID) && (sih->chiprev == 2)) {
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+ if ((sih->chip == BCM4329_CHIP_ID) && (sih->chiprev == 2)) {
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/* Fix for 4329b0 bad LPOM state. */
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W_REG(osh, &cc->regcontrol_addr, 2);
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OR_REG(osh, &cc->regcontrol_data, 0x100);
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@@ -2090,7 +2090,7 @@ void si_pmu_otp_power(si_t *sih, struct osl_info *osh, bool on)
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cc = si_setcoreidx(sih, SI_CC_IDX);
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ASSERT(cc != NULL);
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM4329_CHIP_ID:
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rsrcs = PMURES_BIT(RES4329_OTP_PU);
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break;
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@@ -2153,7 +2153,7 @@ void si_pmu_rcal(si_t *sih, struct osl_info *osh)
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cc = si_setcoreidx(sih, SI_CC_IDX);
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ASSERT(cc != NULL);
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM4329_CHIP_ID:{
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u8 rcal_code;
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u32 val;
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@@ -2236,7 +2236,7 @@ void si_pmu_spuravoid(si_t *sih, struct osl_info *osh, u8 spuravoid)
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ASSERT(cc != NULL);
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/* force the HT off */
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- if (CHIPID(sih->chip) == BCM4336_CHIP_ID) {
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+ if (sih->chip == BCM4336_CHIP_ID) {
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tmp = R_REG(osh, &cc->max_res_mask);
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tmp &= ~RES4336_HT_AVAIL;
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W_REG(osh, &cc->max_res_mask, tmp);
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@@ -2250,7 +2250,7 @@ void si_pmu_spuravoid(si_t *sih, struct osl_info *osh, u8 spuravoid)
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si_pmu_spuravoid_pllupdate(sih, cc, osh, spuravoid);
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/* enable HT back on */
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- if (CHIPID(sih->chip) == BCM4336_CHIP_ID) {
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+ if (sih->chip == BCM4336_CHIP_ID) {
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tmp = R_REG(osh, &cc->max_res_mask);
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tmp |= RES4336_HT_AVAIL;
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W_REG(osh, &cc->max_res_mask, tmp);
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@@ -2269,14 +2269,14 @@ si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, struct osl_info *osh,
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u8 bcm5357_bcm43236_p1div[] = { 0x1, 0x5, 0x5 };
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u8 bcm5357_bcm43236_ndiv[] = { 0x30, 0xf6, 0xfc };
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM5357_CHIP_ID:
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case BCM43235_CHIP_ID:
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case BCM43236_CHIP_ID:
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case BCM43238_CHIP_ID:
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/* BCM5357 needs to touch PLL1_PLLCTL[02], so offset PLL0_PLLCTL[02] by 6 */
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- phypll_offset = (CHIPID(sih->chip) == BCM5357_CHIP_ID) ? 6 : 0;
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+ phypll_offset = (sih->chip == BCM5357_CHIP_ID) ? 6 : 0;
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/* RMW only the P1 divider */
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W_REG(osh, &cc->pllcontrol_addr,
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@@ -2468,7 +2468,7 @@ bool si_pmu_is_otp_powered(si_t *sih, struct osl_info *osh)
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cc = si_setcoreidx(sih, SI_CC_IDX);
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ASSERT(cc != NULL);
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM4329_CHIP_ID:
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st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4329_OTP_PU))
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!= 0;
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@@ -2553,7 +2553,7 @@ void si_pmu_swreg_init(si_t *sih, struct osl_info *osh)
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{
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ASSERT(sih->cccaps & CC_CAP_PMU);
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM4336_CHIP_ID:
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/* Reduce CLDO PWM output voltage to 1.2V */
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si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_PWM, 0xe);
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@@ -2579,7 +2579,7 @@ void si_pmu_radio_enable(si_t *sih, bool enable)
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{
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ASSERT(sih->cccaps & CC_CAP_PMU);
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- switch (CHIPID(sih->chip)) {
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+ switch (sih->chip) {
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case BCM4319_CHIP_ID:
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if (enable)
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si_write_wrapperreg(sih, AI_OOBSELOUTB74,
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