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@@ -111,12 +111,21 @@ static struct clk div3_clk = {
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.parent = &pll_clk,
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};
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+/* External input clock (pin name: FSIMCKA/FSIMCKB ) */
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+struct clk sh7724_fsimcka_clk = {
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+};
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+
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+struct clk sh7724_fsimckb_clk = {
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+};
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+
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static struct clk *main_clks[] = {
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&r_clk,
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&extal_clk,
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&fll_clk,
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&pll_clk,
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&div3_clk,
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+ &sh7724_fsimcka_clk,
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+ &sh7724_fsimckb_clk,
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};
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static void div4_kick(struct clk *clk)
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@@ -154,16 +163,38 @@ struct clk div4_clks[DIV4_NR] = {
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[DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
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};
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-enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };
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+enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR };
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static struct clk div6_clks[DIV6_NR] = {
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[DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
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- [DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0),
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- [DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0),
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[DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
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[DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
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};
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+enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR };
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+
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+/* Indices are important - they are the actual src selecting values */
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+static struct clk *fclkacr_parent[] = {
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+ [0] = &div3_clk,
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+ [1] = NULL,
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+ [2] = &sh7724_fsimcka_clk,
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+ [3] = NULL,
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+};
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+
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+static struct clk *fclkbcr_parent[] = {
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+ [0] = &div3_clk,
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+ [1] = NULL,
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+ [2] = &sh7724_fsimckb_clk,
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+ [3] = NULL,
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+};
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+
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+static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
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+ [DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0,
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+ fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2),
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+ [DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0,
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+ fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2),
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+};
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+
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static struct clk mstp_clks[HWBLK_NR] = {
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SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
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@@ -240,8 +271,8 @@ static struct clk_lookup lookups[] = {
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/* DIV6 clocks */
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CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
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- CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),
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- CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]),
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+ CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]),
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+ CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]),
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CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
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CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
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@@ -375,6 +406,9 @@ int __init arch_clk_init(void)
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if (!ret)
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ret = sh_clk_div6_register(div6_clks, DIV6_NR);
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+ if (!ret)
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+ ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
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+
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if (!ret)
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ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
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