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@@ -92,6 +92,21 @@
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.endm
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#endif /* CONFIG_M5249 || CONFIG_M5307 */
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+#if defined(CONFIG_M532x)
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+.macro CACHE_ENABLE
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+ movel #0x01000000,%d0 /* invalidate cache cmd */
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+ movec %d0,%CACR /* do invalidate cache */
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+ nop
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+ movel #0x4001C000,%d0 /* set SDRAM cached (write-thru) */
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+ movec %d0,%ACR0
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+ movel #0x00000000,%d0 /* no other regions cached */
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+ movec %d0,%ACR1
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+ movel #0x80000200,%d0 /* setup cache mask */
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+ movec %d0,%CACR /* enable cache */
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+ nop
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+.endm
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+#endif /* CONFIG_M532x */
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+
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#if defined(CONFIG_M5407)
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/*
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* Version 4 cores have a true harvard style separate instruction
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