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@@ -100,13 +100,14 @@ static int omap_check_spurious(unsigned int irq)
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}
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/* XXX: FIQ and additional INTC support (only MPU at the moment) */
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-static void omap_ack_irq(unsigned int irq)
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+static void omap_ack_irq(struct irq_data *d)
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{
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intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
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}
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-static void omap_mask_irq(unsigned int irq)
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+static void omap_mask_irq(struct irq_data *d)
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{
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+ unsigned int irq = d->irq;
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int offset = irq & (~(IRQ_BITS_PER_REG - 1));
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if (cpu_is_omap34xx()) {
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@@ -128,8 +129,9 @@ static void omap_mask_irq(unsigned int irq)
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intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
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}
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-static void omap_unmask_irq(unsigned int irq)
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+static void omap_unmask_irq(struct irq_data *d)
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{
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+ unsigned int irq = d->irq;
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int offset = irq & (~(IRQ_BITS_PER_REG - 1));
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irq &= (IRQ_BITS_PER_REG - 1);
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@@ -137,17 +139,17 @@ static void omap_unmask_irq(unsigned int irq)
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intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
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}
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-static void omap_mask_ack_irq(unsigned int irq)
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+static void omap_mask_ack_irq(struct irq_data *d)
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{
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- omap_mask_irq(irq);
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- omap_ack_irq(irq);
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+ omap_mask_irq(d);
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+ omap_ack_irq(d);
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}
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static struct irq_chip omap_irq_chip = {
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- .name = "INTC",
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- .ack = omap_mask_ack_irq,
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- .mask = omap_mask_irq,
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- .unmask = omap_unmask_irq,
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+ .name = "INTC",
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+ .irq_ack = omap_mask_ack_irq,
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+ .irq_mask = omap_mask_irq,
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+ .irq_unmask = omap_unmask_irq,
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};
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static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
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