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@@ -0,0 +1,458 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
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+ *
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+ * SMP support for BMIPS
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+ */
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+
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+#include <linux/version.h>
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+#include <linux/init.h>
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+#include <linux/sched.h>
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+#include <linux/mm.h>
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+#include <linux/delay.h>
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+#include <linux/smp.h>
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+#include <linux/interrupt.h>
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+#include <linux/spinlock.h>
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+#include <linux/init.h>
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+#include <linux/cpu.h>
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+#include <linux/cpumask.h>
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+#include <linux/reboot.h>
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+#include <linux/io.h>
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+#include <linux/compiler.h>
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+#include <linux/linkage.h>
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+#include <linux/bug.h>
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+#include <linux/kernel.h>
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+
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+#include <asm/time.h>
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+#include <asm/pgtable.h>
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+#include <asm/processor.h>
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+#include <asm/system.h>
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+#include <asm/bootinfo.h>
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+#include <asm/pmon.h>
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+#include <asm/cacheflush.h>
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+#include <asm/tlbflush.h>
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+#include <asm/mipsregs.h>
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+#include <asm/bmips.h>
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+#include <asm/traps.h>
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+#include <asm/barrier.h>
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+
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+static int __maybe_unused max_cpus = 1;
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+
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+/* these may be configured by the platform code */
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+int bmips_smp_enabled = 1;
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+int bmips_cpu_offset;
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+cpumask_t bmips_booted_mask;
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+
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+#ifdef CONFIG_SMP
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+
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+/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
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+unsigned long bmips_smp_boot_sp;
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+unsigned long bmips_smp_boot_gp;
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+
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+static void bmips_send_ipi_single(int cpu, unsigned int action);
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+static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
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+
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+/* SW interrupts 0,1 are used for interprocessor signaling */
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+#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
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+#define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
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+
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+#define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
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+#define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
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+#define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
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+#define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
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+
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+static void __init bmips_smp_setup(void)
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+{
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+ int i;
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+
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+#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
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+ /* arbitration priority */
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+ clear_c0_brcm_cmt_ctrl(0x30);
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+
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+ /* NBK and weak order flags */
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+ set_c0_brcm_config_0(0x30000);
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+
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+ /*
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+ * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
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+ * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
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+ * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
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+ */
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+ change_c0_brcm_cmt_intr(0xf8018000,
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+ (0x02 << 27) | (0x03 << 15));
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+
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+ /* single core, 2 threads (2 pipelines) */
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+ max_cpus = 2;
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+#elif defined(CONFIG_CPU_BMIPS5000)
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+ /* enable raceless SW interrupts */
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+ set_c0_brcm_config(0x03 << 22);
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+
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+ /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
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+ change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
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+
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+ /* N cores, 2 threads per core */
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+ max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
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+
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+ /* clear any pending SW interrupts */
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+ for (i = 0; i < max_cpus; i++) {
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+ write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
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+ write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
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+ }
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+#endif
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+
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+ if (!bmips_smp_enabled)
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+ max_cpus = 1;
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+
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+ /* this can be overridden by the BSP */
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+ if (!board_ebase_setup)
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+ board_ebase_setup = &bmips_ebase_setup;
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+
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+ for (i = 0; i < max_cpus; i++) {
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+ __cpu_number_map[i] = 1;
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+ __cpu_logical_map[i] = 1;
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+ set_cpu_possible(i, 1);
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+ set_cpu_present(i, 1);
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+ }
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+}
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+
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+/*
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+ * IPI IRQ setup - runs on CPU0
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+ */
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+static void bmips_prepare_cpus(unsigned int max_cpus)
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+{
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+ if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
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+ "smp_ipi0", NULL))
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+ panic("Can't request IPI0 interrupt\n");
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+ if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
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+ "smp_ipi1", NULL))
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+ panic("Can't request IPI1 interrupt\n");
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+}
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+
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+/*
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+ * Tell the hardware to boot CPUx - runs on CPU0
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+ */
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+static void bmips_boot_secondary(int cpu, struct task_struct *idle)
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+{
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+ bmips_smp_boot_sp = __KSTK_TOS(idle);
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+ bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
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+ mb();
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+
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+ /*
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+ * Initial boot sequence for secondary CPU:
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+ * bmips_reset_nmi_vec @ a000_0000 ->
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+ * bmips_smp_entry ->
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+ * plat_wired_tlb_setup (cached function call; optional) ->
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+ * start_secondary (cached jump)
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+ *
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+ * Warm restart sequence:
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+ * play_dead WAIT loop ->
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+ * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
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+ * eret to play_dead ->
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+ * bmips_secondary_reentry ->
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+ * start_secondary
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+ */
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+
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+ pr_info("SMP: Booting CPU%d...\n", cpu);
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+
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+ if (cpumask_test_cpu(cpu, &bmips_booted_mask))
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+ bmips_send_ipi_single(cpu, 0);
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+ else {
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+#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
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+ set_c0_brcm_cmt_ctrl(0x01);
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+#elif defined(CONFIG_CPU_BMIPS5000)
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+ if (cpu & 0x01)
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+ write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
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+ else {
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+ /*
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+ * core N thread 0 was already booted; just
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+ * pulse the NMI line
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+ */
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+ bmips_write_zscm_reg(0x210, 0xc0000000);
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+ udelay(10);
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+ bmips_write_zscm_reg(0x210, 0x00);
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+ }
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+#endif
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+ cpumask_set_cpu(cpu, &bmips_booted_mask);
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+ }
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+}
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+
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+/*
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+ * Early setup - runs on secondary CPU after cache probe
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+ */
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+static void bmips_init_secondary(void)
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+{
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+ /* move NMI vector to kseg0, in case XKS01 is enabled */
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+
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+#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
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+ void __iomem *cbr = BMIPS_GET_CBR();
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+ unsigned long old_vec;
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+
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+ old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
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+ __raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
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+
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+ clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
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+#elif defined(CONFIG_CPU_BMIPS5000)
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+ write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
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+ (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
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+
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+ write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
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+#endif
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+
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+ /* make sure there won't be a timer interrupt for a little while */
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+ write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
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+
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+ irq_enable_hazard();
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+ set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
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+ irq_enable_hazard();
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+}
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+
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+/*
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+ * Late setup - runs on secondary CPU before entering the idle loop
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+ */
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+static void bmips_smp_finish(void)
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+{
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+ pr_info("SMP: CPU%d is running\n", smp_processor_id());
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+}
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+
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+/*
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+ * Runs on CPU0 after all CPUs have been booted
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+ */
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+static void bmips_cpus_done(void)
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+{
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+}
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+
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+#if defined(CONFIG_CPU_BMIPS5000)
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+
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+/*
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+ * BMIPS5000 raceless IPIs
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+ *
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+ * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
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+ * IPI0 is used for SMP_RESCHEDULE_YOURSELF
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+ * IPI1 is used for SMP_CALL_FUNCTION
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+ */
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+
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+static void bmips_send_ipi_single(int cpu, unsigned int action)
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+{
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+ write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
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+}
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+
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+static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
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+{
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+ int action = irq - IPI0_IRQ;
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+
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+ write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
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+
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+ if (action == 0)
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+ scheduler_ipi();
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+ else
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+ smp_call_function_interrupt();
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+
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+ return IRQ_HANDLED;
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+}
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+
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+#else
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+
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+/*
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+ * BMIPS43xx racey IPIs
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+ *
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+ * We use one inbound SW IRQ for each CPU.
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+ *
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+ * A spinlock must be held in order to keep CPUx from accidentally clearing
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+ * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
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+ * same spinlock is used to protect the action masks.
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+ */
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+
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+static DEFINE_SPINLOCK(ipi_lock);
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+static DEFINE_PER_CPU(int, ipi_action_mask);
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+
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+static void bmips_send_ipi_single(int cpu, unsigned int action)
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+{
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&ipi_lock, flags);
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+ set_c0_cause(cpu ? C_SW1 : C_SW0);
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+ per_cpu(ipi_action_mask, cpu) |= action;
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+ irq_enable_hazard();
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+ spin_unlock_irqrestore(&ipi_lock, flags);
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+}
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+
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+static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
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+{
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+ unsigned long flags;
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+ int action, cpu = irq - IPI0_IRQ;
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+
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+ spin_lock_irqsave(&ipi_lock, flags);
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+ action = __get_cpu_var(ipi_action_mask);
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+ per_cpu(ipi_action_mask, cpu) = 0;
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+ clear_c0_cause(cpu ? C_SW1 : C_SW0);
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+ spin_unlock_irqrestore(&ipi_lock, flags);
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+
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+ if (action & SMP_RESCHEDULE_YOURSELF)
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+ scheduler_ipi();
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+ if (action & SMP_CALL_FUNCTION)
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+ smp_call_function_interrupt();
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+
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+ return IRQ_HANDLED;
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+}
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+
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+#endif /* BMIPS type */
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+
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+static void bmips_send_ipi_mask(const struct cpumask *mask,
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+ unsigned int action)
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+{
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+ unsigned int i;
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+
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+ for_each_cpu(i, mask)
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+ bmips_send_ipi_single(i, action);
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+}
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+
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+#ifdef CONFIG_HOTPLUG_CPU
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+
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+static int bmips_cpu_disable(void)
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+{
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+ unsigned int cpu = smp_processor_id();
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+
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+ if (cpu == 0)
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+ return -EBUSY;
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+
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+ pr_info("SMP: CPU%d is offline\n", cpu);
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+
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+ cpu_clear(cpu, cpu_online_map);
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+ cpu_clear(cpu, cpu_callin_map);
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+
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+ local_flush_tlb_all();
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+ local_flush_icache_range(0, ~0);
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+
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+ return 0;
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+}
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+
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+static void bmips_cpu_die(unsigned int cpu)
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+{
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+}
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+
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+void __ref play_dead(void)
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+{
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+ idle_task_exit();
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+
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+ /* flush data cache */
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+ _dma_cache_wback_inv(0, ~0);
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+
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+ /*
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+ * Wakeup is on SW0 or SW1; disable everything else
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+ * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
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+ * IRQ handlers; this clears ST0_IE and returns immediately.
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+ */
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+ clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
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+ change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
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+ IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
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+ irq_disable_hazard();
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+
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+ /*
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+ * wait for SW interrupt from bmips_boot_secondary(), then jump
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+ * back to start_secondary()
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+ */
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+ __asm__ __volatile__(
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+ " wait\n"
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+ " j bmips_secondary_reentry\n"
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+ : : : "memory");
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+}
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+
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+#endif /* CONFIG_HOTPLUG_CPU */
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+
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+struct plat_smp_ops bmips_smp_ops = {
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+ .smp_setup = bmips_smp_setup,
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+ .prepare_cpus = bmips_prepare_cpus,
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+ .boot_secondary = bmips_boot_secondary,
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+ .smp_finish = bmips_smp_finish,
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+ .init_secondary = bmips_init_secondary,
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+ .cpus_done = bmips_cpus_done,
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+ .send_ipi_single = bmips_send_ipi_single,
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+ .send_ipi_mask = bmips_send_ipi_mask,
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+#ifdef CONFIG_HOTPLUG_CPU
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+ .cpu_disable = bmips_cpu_disable,
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+ .cpu_die = bmips_cpu_die,
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+#endif
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+};
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+
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+#endif /* CONFIG_SMP */
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+
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+/***********************************************************************
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+ * BMIPS vector relocation
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+ * This is primarily used for SMP boot, but it is applicable to some
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+ * UP BMIPS systems as well.
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+ ***********************************************************************/
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+
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+static void __cpuinit bmips_wr_vec(unsigned long dst, char *start, char *end)
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+{
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+ memcpy((void *)dst, start, end - start);
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+ dma_cache_wback((unsigned long)start, end - start);
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+ local_flush_icache_range(dst, dst + (end - start));
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|
|
+ instruction_hazard();
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|
|
+}
|
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|
+
|
|
|
+static inline void __cpuinit bmips_nmi_handler_setup(void)
|
|
|
+{
|
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|
+ bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
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|
|
+ &bmips_reset_nmi_vec_end);
|
|
|
+ bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
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|
|
+ &bmips_smp_int_vec_end);
|
|
|
+}
|
|
|
+
|
|
|
+void __cpuinit bmips_ebase_setup(void)
|
|
|
+{
|
|
|
+ unsigned long new_ebase = ebase;
|
|
|
+ void __iomem __maybe_unused *cbr;
|
|
|
+
|
|
|
+ BUG_ON(ebase != CKSEG0);
|
|
|
+
|
|
|
+#if defined(CONFIG_CPU_BMIPS4350)
|
|
|
+ /*
|
|
|
+ * BMIPS4350 cannot relocate the normal vectors, but it
|
|
|
+ * can relocate the BEV=1 vectors. So CPU1 starts up at
|
|
|
+ * the relocated BEV=1, IV=0 general exception vector @
|
|
|
+ * 0xa000_0380.
|
|
|
+ *
|
|
|
+ * set_uncached_handler() is used here because:
|
|
|
+ * - CPU1 will run this from uncached space
|
|
|
+ * - None of the cacheflush functions are set up yet
|
|
|
+ */
|
|
|
+ set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
|
|
|
+ &bmips_smp_int_vec, 0x80);
|
|
|
+ __sync();
|
|
|
+ return;
|
|
|
+#elif defined(CONFIG_CPU_BMIPS4380)
|
|
|
+ /*
|
|
|
+ * 0x8000_0000: reset/NMI (initially in kseg1)
|
|
|
+ * 0x8000_0400: normal vectors
|
|
|
+ */
|
|
|
+ new_ebase = 0x80000400;
|
|
|
+ cbr = BMIPS_GET_CBR();
|
|
|
+ __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
|
|
|
+ __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
|
|
|
+#elif defined(CONFIG_CPU_BMIPS5000)
|
|
|
+ /*
|
|
|
+ * 0x8000_0000: reset/NMI (initially in kseg1)
|
|
|
+ * 0x8000_1000: normal vectors
|
|
|
+ */
|
|
|
+ new_ebase = 0x80001000;
|
|
|
+ write_c0_brcm_bootvec(0xa0088008);
|
|
|
+ write_c0_ebase(new_ebase);
|
|
|
+ if (max_cpus > 2)
|
|
|
+ bmips_write_zscm_reg(0xa0, 0xa008a008);
|
|
|
+#else
|
|
|
+ return;
|
|
|
+#endif
|
|
|
+ board_nmi_handler_setup = &bmips_nmi_handler_setup;
|
|
|
+ ebase = new_ebase;
|
|
|
+}
|
|
|
+
|
|
|
+asmlinkage void __weak plat_wired_tlb_setup(void)
|
|
|
+{
|
|
|
+ /*
|
|
|
+ * Called when starting/restarting a secondary CPU.
|
|
|
+ * Kernel stacks and other important data might only be accessible
|
|
|
+ * once the wired entries are present.
|
|
|
+ */
|
|
|
+}
|
Kevin Cernekee