Răsfoiți Sursa

i.MX3: Fix compiler warnings

Fix some base address declaration by adding a cast.

Signed-off-by: Luotao Fu <l.fu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Luotao Fu 16 ani în urmă
părinte
comite
defa8c309d

+ 4 - 2
arch/arm/mach-mx3/iomux.c

@@ -43,7 +43,8 @@ static DEFINE_SPINLOCK(gpio_mux_lock);
  */
  */
 int mxc_iomux_mode(unsigned int pin_mode)
 int mxc_iomux_mode(unsigned int pin_mode)
 {
 {
-	u32 reg, field, l, mode, ret = 0;
+	u32 field, l, mode, ret = 0;
+	void __iomem *reg;
 
 
 	reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
 	reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
 	field = pin_mode & 0x3;
 	field = pin_mode & 0x3;
@@ -70,7 +71,8 @@ EXPORT_SYMBOL(mxc_iomux_mode);
  */
  */
 void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
 void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
 {
 {
-	u32 reg, field, l;
+	u32 field, l;
+	void __iomem *reg;
 
 
 	reg = IOMUXSW_PAD_CTL + (pin + 2) / 3;
 	reg = IOMUXSW_PAD_CTL + (pin + 2) / 3;
 	field = (pin + 2) % 3;
 	field = (pin + 2) % 3;

+ 1 - 1
arch/arm/plat-mxc/include/mach/clock.h

@@ -39,7 +39,7 @@ struct clk {
 	/* Register bit position for clock's enable/disable control. */
 	/* Register bit position for clock's enable/disable control. */
 	u8 enable_shift;
 	u8 enable_shift;
 	/* Register address for clock's enable/disable control. */
 	/* Register address for clock's enable/disable control. */
-	u32 enable_reg;
+	void __iomem *enable_reg;
 	u32 flags;
 	u32 flags;
 	/* get the current clock rate (always a fresh value) */
 	/* get the current clock rate (always a fresh value) */
 	unsigned long (*get_rate) (struct clk *);
 	unsigned long (*get_rate) (struct clk *);

+ 1 - 0
arch/arm/plat-mxc/include/mach/mx27.h

@@ -128,6 +128,7 @@
  * it returns 0xDEADBEEF
  * it returns 0xDEADBEEF
  */
  */
 #define IO_ADDRESS(x)   \
 #define IO_ADDRESS(x)   \
+	(void __iomem *) \
 	(((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
 	(((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
 		AIPI_IO_ADDRESS(x) : \
 		AIPI_IO_ADDRESS(x) : \
 	((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
 	((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \

+ 1 - 0
arch/arm/plat-mxc/include/mach/mx31.h

@@ -198,6 +198,7 @@
  * it returns 0xDEADBEEF
  * it returns 0xDEADBEEF
  */
  */
 #define IO_ADDRESS(x)   \
 #define IO_ADDRESS(x)   \
+	(void __iomem *) \
 	(((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
 	(((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
 	((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
 	((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
 	((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
 	((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\