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@@ -35,6 +35,17 @@ int tegra_cpu_process_id;
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int tegra_core_process_id;
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enum tegra_revision tegra_revision;
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+/* The BCT to use at boot is specified by board straps that can be read
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+ * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
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+ */
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+int tegra_bct_strapping;
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+
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+#define STRAP_OPT 0x008
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+#define GMI_AD0 (1 << 4)
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+#define GMI_AD1 (1 << 5)
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+#define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
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+#define RAM_CODE_SHIFT 4
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+
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static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
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[TEGRA_REVISION_UNKNOWN] = "unknown",
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[TEGRA_REVISION_A01] = "A01",
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@@ -93,6 +104,9 @@ void tegra_init_fuse(void)
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reg = tegra_fuse_readl(FUSE_SPARE_BIT);
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tegra_core_process_id = (reg >> 12) & 3;
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+ reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
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+ tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
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+
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tegra_revision = tegra_get_revision();
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pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
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