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drm/i915: implement a media hang w/a

Contrary to the other clock gating w/a in GEN6_UCGCTL1, this one is
actually documented in Bspec, vol1g "GT Interface Registers [SNB]",
Section 1.5.1 "UCGCTL1 - Unit Level Clock Gating Control 1".

Supposedly this can prevent hangs on the media ring.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter 13 years ago
parent
767878908e
commit
de4a8bd162
2 changed files with 3 additions and 1 deletions
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  1. 1 0
      drivers/gpu/drm/i915/i915_reg.h
  2. 2 1
      drivers/gpu/drm/i915/intel_display.c

+ 1 - 0
drivers/gpu/drm/i915/i915_reg.h
View File 

@@ -3893,6 +3893,7 @@
 
 
 #define GEN6_UCGCTL1				0x9400
 
 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
 
+# define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
 
 
 #define GEN6_UCGCTL2				0x9404
 
 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)

+ 2 - 1
drivers/gpu/drm/i915/intel_display.c
View File 

@@ -8880,7 +8880,8 @@ static void gen6_init_clock_gating(struct drm_device *dev)
 
 
 	I915_WRITE(GEN6_UCGCTL1,
 
 		   I915_READ(GEN6_UCGCTL1) |
 
-		   GEN6_BLBUNIT_CLOCK_GATE_DISABLE);
 
+		   GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
 
+		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
 
 
 	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
 
 	 * gating disable must be set.  Failure to set it results in