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@@ -31,11 +31,16 @@
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#include <asm/io.h>
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#include "bttvp.h"
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-/* Offset from line sync pulse leading edge (0H) in 1 / sampling_rate:
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- bt8x8 /HRESET pulse starts at 0H and has length 64 / fCLKx1 (E|O_VTC
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- HSFMT = 0). VBI_HDELAY (always 0) is an offset from the trailing edge
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- of /HRESET in 1 / fCLKx1, and the sampling_rate tvnorm->Fsc is fCLKx2. */
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-#define VBI_OFFSET ((64 + 0) * 2)
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+/* Offset from line sync pulse leading edge (0H) to start of VBI capture,
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+ in fCLKx2 pixels. According to the datasheet, VBI capture starts
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+ VBI_HDELAY fCLKx1 pixels from the tailing edgeof /HRESET, and /HRESET
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+ is 64 fCLKx1 pixels wide. VBI_HDELAY is set to 0, so this should be
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+ (64 + 0) * 2 = 128 fCLKx2 pixels. But it's not! The datasheet is
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+ Just Plain Wrong. The real value appears to be different for
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+ different revisions of the bt8x8 chips, and to be affected by the
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+ horizontal scaling factor. Experimentally, the value is measured
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+ to be about 244. */
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+#define VBI_OFFSET 244
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#define VBI_DEFLINES 16
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#define VBI_MAXLINES 32
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