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@@ -266,8 +266,6 @@
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#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
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#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
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#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
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#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
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-#define FH_RSCSR_FRAME_SIZE_MSK (0x00003FFF) /* bits 0-13 */
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-
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/**
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/**
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* Rx Shared Status Registers (RSSR)
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* Rx Shared Status Registers (RSSR)
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*
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*
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@@ -422,10 +420,6 @@
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#define RX_FREE_BUFFERS 64
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#define RX_FREE_BUFFERS 64
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#define RX_LOW_WATERMARK 8
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#define RX_LOW_WATERMARK 8
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-/* Size of one Rx buffer in host DRAM */
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-#define IWL_RX_BUF_SIZE_4K (4 * 1024)
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-#define IWL_RX_BUF_SIZE_8K (8 * 1024)
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-
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/**
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/**
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* struct iwl_rb_status - reseve buffer status
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* struct iwl_rb_status - reseve buffer status
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* host memory mapped FH registers
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* host memory mapped FH registers
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@@ -508,4 +502,16 @@ struct iwl_tfd {
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/* Keep Warm Size */
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/* Keep Warm Size */
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#define IWL_KW_SIZE 0x1000 /* 4k */
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#define IWL_KW_SIZE 0x1000 /* 4k */
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+/* Fixed (non-configurable) rx data from phy */
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+
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+/**
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+ * struct iwlagn_schedq_bc_tbl scheduler byte count table
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+ * base physical address provided by SCD_DRAM_BASE_ADDR
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+ * @tfd_offset 0-12 - tx command byte count
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+ * 12-16 - station index
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+ */
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+struct iwlagn_scd_bc_tbl {
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+ __le16 tfd_offset[TFD_QUEUE_BC_SIZE];
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+} __packed;
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+
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#endif /* !__iwl_fh_h__ */
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#endif /* !__iwl_fh_h__ */
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