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@@ -90,6 +90,7 @@
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#define PCH_PHUB_INTPIN_REG_WPERMIT_REG3 0x002C
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#define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE 0x0040
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#define CLKCFG_REG_OFFSET 0x500
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+#define FUNCSEL_REG_OFFSET 0x508
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#define PCH_PHUB_OROM_SIZE 15360
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@@ -108,6 +109,7 @@
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* @intpin_reg_wpermit_reg3: INTPIN_REG_WPERMIT register 3 val
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* @int_reduce_control_reg: INT_REDUCE_CONTROL registers val
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* @clkcfg_reg: CLK CFG register val
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+ * @funcsel_reg: Function select register value
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* @pch_phub_base_address: Register base address
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* @pch_phub_extrom_base_address: external rom base address
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* @pch_mac_start_address: MAC address area start address
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@@ -128,6 +130,7 @@ struct pch_phub_reg {
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u32 intpin_reg_wpermit_reg3;
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u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG];
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u32 clkcfg_reg;
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+ u32 funcsel_reg;
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void __iomem *pch_phub_base_address;
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void __iomem *pch_phub_extrom_base_address;
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u32 pch_mac_start_address;
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@@ -211,6 +214,8 @@ static void pch_phub_save_reg_conf(struct pci_dev *pdev)
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__func__, i, chip->int_reduce_control_reg[i]);
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}
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chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
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+ if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
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+ chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET);
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}
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/* pch_phub_restore_reg_conf - restore register configuration */
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@@ -271,6 +276,8 @@ static void pch_phub_restore_reg_conf(struct pci_dev *pdev)
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}
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iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
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+ if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
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+ iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET);
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}
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/**
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