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@@ -544,6 +544,28 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w,
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switch (event) {
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case SND_SOC_DAPM_POST_PMU:
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+ /*
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+ * For simplicity set the DSP clock rate to be the
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+ * SYSCLK rate rather than making it configurable.
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+ */
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+ ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
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+ if (ret != 0) {
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+ adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
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+ ret);
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+ return ret;
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+ }
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+ val = (val & ARIZONA_SYSCLK_FREQ_MASK)
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+ >> ARIZONA_SYSCLK_FREQ_SHIFT;
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+
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+ ret = regmap_update_bits(dsp->regmap,
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+ dsp->base + ADSP2_CLOCKING,
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+ ADSP2_CLK_SEL_MASK, val);
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+ if (ret != 0) {
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+ adsp_err(dsp, "Failed to set clock rate: %d\n",
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+ ret);
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+ return ret;
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+ }
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+
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if (dsp->dvfs) {
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ret = regmap_read(dsp->regmap,
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dsp->base + ADSP2_CLOCKING, &val);
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