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@@ -26,6 +26,8 @@
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* fc000000 da000000 16M PCI CFG0
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* fc000000 da000000 16M PCI CFG0
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* fd000000 d8000000 16M PCI I/O
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* fd000000 d8000000 16M PCI I/O
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* fe[0-7]00000 8M per-platform mappings
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* fe[0-7]00000 8M per-platform mappings
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+ * fe900000 80000000 1M SRAM #0 (first MB)
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+ * fea00000 cb400000 1M SCRATCH ring get/put
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* feb00000 c8000000 1M MSF
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* feb00000 c8000000 1M MSF
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* fec00000 df000000 1M PCI CSRs
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* fec00000 df000000 1M PCI CSRs
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* fed00000 de000000 1M PCI CREG
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* fed00000 de000000 1M PCI CREG
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@@ -91,6 +93,14 @@
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#define IXP2000_MSF_VIRT_BASE 0xfeb00000
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#define IXP2000_MSF_VIRT_BASE 0xfeb00000
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#define IXP2000_MSF_SIZE 0x00100000
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#define IXP2000_MSF_SIZE 0x00100000
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+#define IXP2000_SCRATCH_RING_PHYS_BASE 0xcb400000
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+#define IXP2000_SCRATCH_RING_VIRT_BASE 0xfea00000
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+#define IXP2000_SCRATCH_RING_SIZE 0x00100000
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+
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+#define IXP2000_SRAM0_PHYS_BASE 0x80000000
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+#define IXP2000_SRAM0_VIRT_BASE 0xfe900000
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+#define IXP2000_SRAM0_SIZE 0x00100000
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+
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#define IXP2000_PCI_IO_PHYS_BASE 0xd8000000
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#define IXP2000_PCI_IO_PHYS_BASE 0xd8000000
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#define IXP2000_PCI_IO_VIRT_BASE 0xfd000000
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#define IXP2000_PCI_IO_VIRT_BASE 0xfd000000
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#define IXP2000_PCI_IO_SIZE 0x01000000
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#define IXP2000_PCI_IO_SIZE 0x01000000
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