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@@ -414,7 +414,6 @@ struct rtdPrivate {
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/* shadow registers affect other registers, but can't be read back */
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/* The macros below update these on writes */
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- u16 intClearMask; /* interrupt clear mask */
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u8 utcCtrl[4]; /* crtl mode for 3 utc + read back */
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unsigned fifoLen;
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};
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@@ -782,8 +781,7 @@ static irqreturn_t rtd_interrupt(int irq, /* interrupt number (ignored) */
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goto abortTransfer;
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/* clear the interrupt */
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- devpriv->intClearMask = status;
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- writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
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+ writew(status, devpriv->las0 + LAS0_CLEAR);
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readw(devpriv->las0 + LAS0_CLEAR);
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return IRQ_HANDLED;
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@@ -810,8 +808,7 @@ transferDone:
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/* clear the interrupt */
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status = readw(devpriv->las0 + LAS0_IT);
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- devpriv->intClearMask = status;
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- writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
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+ writew(status, devpriv->las0 + LAS0_CLEAR);
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readw(devpriv->las0 + LAS0_CLEAR);
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fifoStatus = readl(devpriv->las0 + LAS0_ADC);
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@@ -1122,8 +1119,7 @@ static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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/* This doesn't seem to work. There is no way to clear an interrupt
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that the priority controller has queued! */
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- devpriv->intClearMask = ~0;
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- writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
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+ writew(~0, devpriv->las0 + LAS0_CLEAR);
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readw(devpriv->las0 + LAS0_CLEAR);
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/* TODO: allow multiple interrupt sources */
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@@ -1308,8 +1304,7 @@ static void rtd_reset(struct comedi_device *dev)
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udelay(100); /* needed? */
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writel(0, devpriv->lcfg + PLX_INTRCS_REG);
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writew(0, devpriv->las0 + LAS0_IT);
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- devpriv->intClearMask = ~0;
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- writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
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+ writew(~0, devpriv->las0 + LAS0_CLEAR);
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readw(devpriv->las0 + LAS0_CLEAR);
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}
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