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@@ -66,14 +66,8 @@
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/* Host Control Registers : Configuration */
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#define CONFIGURATION_REG 0x00
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-/* Host Control Registers : Host without Command 53 finish host*/
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-#define HOST_TO_CARD_EVENT (0x1U << 3)
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-/* Host Control Registers : Host without Command 53 finish host */
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-#define HOST_WO_CMD53_FINISH_HOST (0x1U << 2)
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/* Host Control Registers : Host power up */
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#define HOST_POWER_UP (0x1U << 1)
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-/* Host Control Registers : Host power down */
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-#define HOST_POWER_DOWN (0x1U << 0)
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/* Host Control Registers : Host interrupt mask */
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#define HOST_INT_MASK_REG 0x02
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@@ -93,60 +87,15 @@
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/* Host Control Registers : Host interrupt RSR */
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#define HOST_INT_RSR_REG 0x01
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-/* Host Control Registers : Upload host interrupt RSR */
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-#define UP_LD_HOST_INT_RSR (0x1U)
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/* Host Control Registers : Host interrupt status */
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#define HOST_INT_STATUS_REG 0x28
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-/* Host Control Registers : Upload CRC error */
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-#define UP_LD_CRC_ERR (0x1U << 2)
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-/* Host Control Registers : Upload restart */
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-#define UP_LD_RESTART (0x1U << 1)
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-/* Host Control Registers : Download restart */
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-#define DN_LD_RESTART (0x1U << 0)
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/* Card Control Registers : Card I/O ready */
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#define CARD_IO_READY (0x1U << 3)
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-/* Card Control Registers : CIS card ready */
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-#define CIS_CARD_RDY (0x1U << 2)
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-/* Card Control Registers : Upload card ready */
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-#define UP_LD_CARD_RDY (0x1U << 1)
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/* Card Control Registers : Download card ready */
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#define DN_LD_CARD_RDY (0x1U << 0)
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-/* Card Control Registers : Host interrupt mask register */
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-#define HOST_INTERRUPT_MASK_REG 0x34
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-/* Card Control Registers : Host power interrupt mask */
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-#define HOST_POWER_INT_MASK (0x1U << 3)
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-/* Card Control Registers : Abort card interrupt mask */
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-#define ABORT_CARD_INT_MASK (0x1U << 2)
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-/* Card Control Registers : Upload card interrupt mask */
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-#define UP_LD_CARD_INT_MASK (0x1U << 1)
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-/* Card Control Registers : Download card interrupt mask */
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-#define DN_LD_CARD_INT_MASK (0x1U << 0)
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-
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-/* Card Control Registers : Card interrupt status register */
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-#define CARD_INTERRUPT_STATUS_REG 0x38
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-/* Card Control Registers : Power up interrupt */
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-#define POWER_UP_INT (0x1U << 4)
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-/* Card Control Registers : Power down interrupt */
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-#define POWER_DOWN_INT (0x1U << 3)
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-
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-/* Card Control Registers : Card interrupt RSR register */
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-#define CARD_INTERRUPT_RSR_REG 0x3c
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-/* Card Control Registers : Power up RSR */
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-#define POWER_UP_RSR (0x1U << 4)
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-/* Card Control Registers : Power down RSR */
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-#define POWER_DOWN_RSR (0x1U << 3)
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-
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-/* Host F1 card ready */
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-#define HOST_F1_CARD_RDY 0x0020
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-
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-/* Rx length register */
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-#define CARD_RX_LEN_REG 0x62
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-/* Rx unit register */
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-#define CARD_RX_UNIT_REG 0x63
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-
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/* Max retry number of CMD53 write */
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#define MAX_WRITE_IOMEM_RETRY 2
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