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@@ -1,5 +1,5 @@
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-#ifndef _PPC64_PTRACE_H
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-#define _PPC64_PTRACE_H
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+#ifndef _ASM_POWERPC_PTRACE_H
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+#define _ASM_POWERPC_PTRACE_H
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/*
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* Copyright (C) 2001 PPC64 Team, IBM Corp
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@@ -16,7 +16,7 @@
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* that the overall structure is a multiple of 16 bytes in length.
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*
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* Note that the offsets of the fields in this struct correspond with
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- * the PT_* values below. This simplifies arch/ppc64/kernel/ptrace.c.
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+ * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@@ -30,70 +30,96 @@ struct pt_regs {
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unsigned long gpr[32];
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unsigned long nip;
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unsigned long msr;
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- unsigned long orig_gpr3; /* Used for restarting system calls */
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+ unsigned long orig_gpr3; /* Used for restarting system calls */
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unsigned long ctr;
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unsigned long link;
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unsigned long xer;
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unsigned long ccr;
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- unsigned long softe; /* Soft enabled/disabled */
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- unsigned long trap; /* Reason for being here */
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- unsigned long dar; /* Fault registers */
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- unsigned long dsisr;
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- unsigned long result; /* Result of a system call */
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+#ifdef __powerpc64__
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+ unsigned long softe; /* Soft enabled/disabled */
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+#else
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+ unsigned long mq; /* 601 only (not used at present) */
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+ /* Used on APUS to hold IPL value. */
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+#endif
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+ unsigned long trap; /* Reason for being here */
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+ /* N.B. for critical exceptions on 4xx, the dar and dsisr
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+ fields are overloaded to hold srr0 and srr1. */
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+ unsigned long dar; /* Fault registers */
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+ unsigned long dsisr; /* on 4xx/Book-E used for ESR */
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+ unsigned long result; /* Result of a system call */
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};
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-struct pt_regs32 {
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- unsigned int gpr[32];
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- unsigned int nip;
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- unsigned int msr;
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- unsigned int orig_gpr3; /* Used for restarting system calls */
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- unsigned int ctr;
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- unsigned int link;
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- unsigned int xer;
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- unsigned int ccr;
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- unsigned int mq; /* 601 only (not used at present) */
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- unsigned int trap; /* Reason for being here */
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- unsigned int dar; /* Fault registers */
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- unsigned int dsisr;
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- unsigned int result; /* Result of a system call */
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-};
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+#endif /* __ASSEMBLY__ */
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#ifdef __KERNEL__
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-#define instruction_pointer(regs) ((regs)->nip)
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+#ifdef __powerpc64__
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+
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+#define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */
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+
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+/* Size of dummy stack frame allocated when calling signal handler. */
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+#define __SIGNAL_FRAMESIZE 128
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+#define __SIGNAL_FRAMESIZE32 64
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+
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+#else /* __powerpc64__ */
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+
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+#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
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+
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+/* Size of stack frame allocated when calling signal handler. */
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+#define __SIGNAL_FRAMESIZE 64
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+
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+#endif /* __powerpc64__ */
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+#ifndef __ASSEMBLY__
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+
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+#define instruction_pointer(regs) ((regs)->nip)
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#ifdef CONFIG_SMP
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extern unsigned long profile_pc(struct pt_regs *regs);
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#else
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#define profile_pc(regs) instruction_pointer(regs)
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#endif
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+#ifdef __powerpc64__
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#define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1)
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+#else
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+#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
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+#endif
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#define force_successful_syscall_return() \
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- (current_thread_info()->syscall_noerror = 1)
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+ do { \
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+ current_thread_info()->syscall_noerror = 1; \
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+ } while(0)
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/*
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* We use the least-significant bit of the trap field to indicate
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* whether we have saved the full set of registers, or only a
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* partial set. A 1 there means the partial set.
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+ * On 4xx we use the next bit to indicate whether the exception
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+ * is a critical exception (1 means it is).
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*/
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#define FULL_REGS(regs) (((regs)->trap & 1) == 0)
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+#ifndef __powerpc64__
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+#define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) == 0)
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+#endif /* ! __powerpc64__ */
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#define TRAP(regs) ((regs)->trap & ~0xF)
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+#ifdef __powerpc64__
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#define CHECK_FULL_REGS(regs) BUG_ON(regs->trap & 1)
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-
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-#endif /* __KERNEL__ */
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+#else
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+#define CHECK_FULL_REGS(regs) \
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+do { \
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+ if ((regs)->trap & 1) \
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+ printk(KERN_CRIT "%s: partial register set\n", __FUNCTION__); \
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+} while (0)
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+#endif /* __powerpc64__ */
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#endif /* __ASSEMBLY__ */
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-#define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */
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-
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-/* Size of dummy stack frame allocated when calling signal handler. */
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-#define __SIGNAL_FRAMESIZE 128
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-#define __SIGNAL_FRAMESIZE32 64
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+#endif /* __KERNEL__ */
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/*
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* Offsets used by 'ptrace' system call interface.
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+ * These can't be changed without breaking binary compatibility
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+ * with MkLinux, etc.
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*/
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#define PT_R0 0
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#define PT_R1 1
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@@ -137,18 +163,25 @@ extern unsigned long profile_pc(struct pt_regs *regs);
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#define PT_LNK 36
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#define PT_XER 37
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#define PT_CCR 38
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+#ifndef __powerpc64__
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+#define PT_MQ 39
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+#else
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#define PT_SOFTE 39
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#define PT_TRAP 40
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#define PT_DAR 41
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#define PT_DSISR 42
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#define PT_RESULT 43
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+#endif
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-#define PT_FPR0 48
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+#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
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+
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+#ifndef __powerpc64__
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+
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+#define PT_FPR31 (PT_FPR0 + 2*31)
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+#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
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+
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+#else /* __powerpc64__ */
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-/*
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- * Kernel and userspace will both use this PT_FPSCR value. 32-bit apps will
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- * have visibility to the asm-ppc/ptrace.h header instead of this one.
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- */
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#define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
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#ifdef __KERNEL__
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@@ -165,29 +198,29 @@ extern unsigned long profile_pc(struct pt_regs *regs);
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#define PT_VRSAVE_32 (PT_VR0 + 33*4)
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#endif
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+#endif /* __powerpc64__ */
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+
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/*
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- * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
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- * The transfer totals 34 quadword. Quadwords 0-31 contain the
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- * corresponding vector registers. Quadword 32 contains the vscr as the
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- * last word (offset 12) within that quadword. Quadword 33 contains the
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+ * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
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+ * The transfer totals 34 quadword. Quadwords 0-31 contain the
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+ * corresponding vector registers. Quadword 32 contains the vscr as the
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+ * last word (offset 12) within that quadword. Quadword 33 contains the
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* vrsave as the first word (offset 0) within the quadword.
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*
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- * This definition of the VMX state is compatible with the current PPC32
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- * ptrace interface. This allows signal handling and ptrace to use the same
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- * structures. This also simplifies the implementation of a bi-arch
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+ * This definition of the VMX state is compatible with the current PPC32
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+ * ptrace interface. This allows signal handling and ptrace to use the same
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+ * structures. This also simplifies the implementation of a bi-arch
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* (combined (32- and 64-bit) gdb.
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*/
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#define PTRACE_GETVRREGS 18
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#define PTRACE_SETVRREGS 19
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-/*
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- * While we dont have 64bit book E processors, we need to reserve the
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- * relevant ptrace calls for 32bit compatibility.
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- */
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-#if 0
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-#define PTRACE_GETEVRREGS 20
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-#define PTRACE_SETEVRREGS 21
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-#endif
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+#ifndef __powerpc64__
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+/* Get/set all the upper 32-bits of the SPE registers, accumulator, and
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+ * spefscr, in one go */
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+#define PTRACE_GETEVRREGS 20
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+#define PTRACE_SETEVRREGS 21
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+#endif /* __powerpc64__ */
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/*
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* Get or set a debug register. The first 16 are DABR registers and the
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@@ -196,6 +229,7 @@ extern unsigned long profile_pc(struct pt_regs *regs);
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#define PTRACE_GET_DEBUGREG 25
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#define PTRACE_SET_DEBUGREG 26
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+#ifdef __powerpc64__
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/* Additional PTRACE requests implemented on PowerPC. */
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#define PPC_PTRACE_GETREGS 0x99 /* Get GPRs 0 - 31 */
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#define PPC_PTRACE_SETREGS 0x98 /* Set GPRs 0 - 31 */
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@@ -209,5 +243,6 @@ extern unsigned long profile_pc(struct pt_regs *regs);
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#define PPC_PTRACE_POKEDATA_3264 0x92
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#define PPC_PTRACE_PEEKUSR_3264 0x91
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#define PPC_PTRACE_POKEUSR_3264 0x90
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+#endif /* __powerpc64__ */
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-#endif /* _PPC64_PTRACE_H */
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+#endif /* _ASM_POWERPC_PTRACE_H */
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