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@@ -1,12 +1,13 @@
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-/* linux/drivers/usb/phy/samsung-usbphy.c
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+/* linux/drivers/usb/phy/phy-samsung-usb.c
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Praveen Paneri <p.paneri@samsung.com>
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*
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- * Samsung USB2.0 PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and
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- * OHCI-EXYNOS controllers.
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+ * Samsung USB-PHY helper driver with common function calls;
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+ * interacts with Samsung USB 2.0 PHY controller driver and later
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+ * with Samsung USB 3.0 PHY driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@@ -21,233 +22,16 @@
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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-#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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-#include <linux/usb/otg.h>
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#include <linux/usb/samsung_usb_phy.h>
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-#include <linux/platform_data/samsung-usbphy.h>
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-/* Register definitions */
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+#include "phy-samsung-usb.h"
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-#define SAMSUNG_PHYPWR (0x00)
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-
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-#define PHYPWR_NORMAL_MASK (0x19 << 0)
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-#define PHYPWR_OTG_DISABLE (0x1 << 4)
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-#define PHYPWR_ANALOG_POWERDOWN (0x1 << 3)
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-#define PHYPWR_FORCE_SUSPEND (0x1 << 1)
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-/* For Exynos4 */
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-#define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0)
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-#define PHYPWR_SLEEP_PHY0 (0x1 << 5)
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-
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-#define SAMSUNG_PHYCLK (0x04)
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-
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-#define PHYCLK_MODE_USB11 (0x1 << 6)
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-#define PHYCLK_EXT_OSC (0x1 << 5)
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-#define PHYCLK_COMMON_ON_N (0x1 << 4)
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-#define PHYCLK_ID_PULL (0x1 << 2)
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-#define PHYCLK_CLKSEL_MASK (0x3 << 0)
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-#define PHYCLK_CLKSEL_48M (0x0 << 0)
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-#define PHYCLK_CLKSEL_12M (0x2 << 0)
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-#define PHYCLK_CLKSEL_24M (0x3 << 0)
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-
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-#define SAMSUNG_RSTCON (0x08)
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-
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-#define RSTCON_PHYLINK_SWRST (0x1 << 2)
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-#define RSTCON_HLINK_SWRST (0x1 << 1)
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-#define RSTCON_SWRST (0x1 << 0)
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-
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-/* EXYNOS5 */
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-#define EXYNOS5_PHY_HOST_CTRL0 (0x00)
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-
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-#define HOST_CTRL0_PHYSWRSTALL (0x1 << 31)
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-
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-#define HOST_CTRL0_REFCLKSEL_MASK (0x3 << 19)
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-#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19)
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-#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19)
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-#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19)
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-
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-#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
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-#define HOST_CTRL0_FSEL(_x) ((_x) << 16)
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-
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-#define FSEL_CLKSEL_50M (0x7)
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-#define FSEL_CLKSEL_24M (0x5)
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-#define FSEL_CLKSEL_20M (0x4)
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-#define FSEL_CLKSEL_19200K (0x3)
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-#define FSEL_CLKSEL_12M (0x2)
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-#define FSEL_CLKSEL_10M (0x1)
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-#define FSEL_CLKSEL_9600K (0x0)
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-
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-#define HOST_CTRL0_TESTBURNIN (0x1 << 11)
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-#define HOST_CTRL0_RETENABLE (0x1 << 10)
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-#define HOST_CTRL0_COMMONON_N (0x1 << 9)
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-#define HOST_CTRL0_SIDDQ (0x1 << 6)
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-#define HOST_CTRL0_FORCESLEEP (0x1 << 5)
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-#define HOST_CTRL0_FORCESUSPEND (0x1 << 4)
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-#define HOST_CTRL0_WORDINTERFACE (0x1 << 3)
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-#define HOST_CTRL0_UTMISWRST (0x1 << 2)
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-#define HOST_CTRL0_LINKSWRST (0x1 << 1)
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-#define HOST_CTRL0_PHYSWRST (0x1 << 0)
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-
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-#define EXYNOS5_PHY_HOST_TUNE0 (0x04)
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-
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-#define EXYNOS5_PHY_HSIC_CTRL1 (0x10)
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-
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-#define EXYNOS5_PHY_HSIC_TUNE1 (0x14)
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-
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-#define EXYNOS5_PHY_HSIC_CTRL2 (0x20)
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-
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-#define EXYNOS5_PHY_HSIC_TUNE2 (0x24)
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-
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-#define HSIC_CTRL_REFCLKSEL_MASK (0x3 << 23)
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-#define HSIC_CTRL_REFCLKSEL (0x2 << 23)
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-
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-#define HSIC_CTRL_REFCLKDIV_MASK (0x7f << 16)
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-#define HSIC_CTRL_REFCLKDIV(_x) ((_x) << 16)
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-#define HSIC_CTRL_REFCLKDIV_12 (0x24 << 16)
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-#define HSIC_CTRL_REFCLKDIV_15 (0x1c << 16)
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-#define HSIC_CTRL_REFCLKDIV_16 (0x1a << 16)
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-#define HSIC_CTRL_REFCLKDIV_19_2 (0x15 << 16)
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-#define HSIC_CTRL_REFCLKDIV_20 (0x14 << 16)
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-
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-#define HSIC_CTRL_SIDDQ (0x1 << 6)
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-#define HSIC_CTRL_FORCESLEEP (0x1 << 5)
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-#define HSIC_CTRL_FORCESUSPEND (0x1 << 4)
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-#define HSIC_CTRL_WORDINTERFACE (0x1 << 3)
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-#define HSIC_CTRL_UTMISWRST (0x1 << 2)
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-#define HSIC_CTRL_PHYSWRST (0x1 << 0)
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-
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-#define EXYNOS5_PHY_HOST_EHCICTRL (0x30)
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-
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-#define HOST_EHCICTRL_ENAINCRXALIGN (0x1 << 29)
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-#define HOST_EHCICTRL_ENAINCR4 (0x1 << 28)
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-#define HOST_EHCICTRL_ENAINCR8 (0x1 << 27)
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-#define HOST_EHCICTRL_ENAINCR16 (0x1 << 26)
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-
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-#define EXYNOS5_PHY_HOST_OHCICTRL (0x34)
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-
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-#define HOST_OHCICTRL_SUSPLGCY (0x1 << 3)
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-#define HOST_OHCICTRL_APPSTARTCLK (0x1 << 2)
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-#define HOST_OHCICTRL_CNTSEL (0x1 << 1)
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-#define HOST_OHCICTRL_CLKCKTRST (0x1 << 0)
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-
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-#define EXYNOS5_PHY_OTG_SYS (0x38)
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-
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-#define OTG_SYS_PHYLINK_SWRESET (0x1 << 14)
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-#define OTG_SYS_LINKSWRST_UOTG (0x1 << 13)
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-#define OTG_SYS_PHY0_SWRST (0x1 << 12)
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-
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-#define OTG_SYS_REFCLKSEL_MASK (0x3 << 9)
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-#define OTG_SYS_REFCLKSEL_XTAL (0x0 << 9)
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-#define OTG_SYS_REFCLKSEL_EXTL (0x1 << 9)
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-#define OTG_SYS_REFCLKSEL_CLKCORE (0x2 << 9)
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-
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-#define OTG_SYS_IDPULLUP_UOTG (0x1 << 8)
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-#define OTG_SYS_COMMON_ON (0x1 << 7)
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-
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-#define OTG_SYS_FSEL_MASK (0x7 << 4)
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-#define OTG_SYS_FSEL(_x) ((_x) << 4)
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-
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-#define OTG_SYS_FORCESLEEP (0x1 << 3)
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-#define OTG_SYS_OTGDISABLE (0x1 << 2)
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-#define OTG_SYS_SIDDQ_UOTG (0x1 << 1)
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-#define OTG_SYS_FORCESUSPEND (0x1 << 0)
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-
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-#define EXYNOS5_PHY_OTG_TUNE (0x40)
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-
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-#ifndef MHZ
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-#define MHZ (1000*1000)
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-#endif
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-
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-#ifndef KHZ
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-#define KHZ (1000)
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-#endif
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-
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-#define EXYNOS_USBHOST_PHY_CTRL_OFFSET (0x4)
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-#define S3C64XX_USBPHY_ENABLE (0x1 << 16)
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-#define EXYNOS_USBPHY_ENABLE (0x1 << 0)
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-#define EXYNOS_USB20PHY_CFG_HOST_LINK (0x1 << 0)
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-
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-enum samsung_cpu_type {
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- TYPE_S3C64XX,
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- TYPE_EXYNOS4210,
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- TYPE_EXYNOS5250,
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-};
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-
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-/*
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- * struct samsung_usbphy_drvdata - driver data for various SoC variants
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- * @cpu_type: machine identifier
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- * @devphy_en_mask: device phy enable mask for PHY CONTROL register
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- * @hostphy_en_mask: host phy enable mask for PHY CONTROL register
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- * @devphy_reg_offset: offset to DEVICE PHY CONTROL register from
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- * mapped address of system controller.
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- * @hostphy_reg_offset: offset to HOST PHY CONTROL register from
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- * mapped address of system controller.
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- *
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- * Here we have a separate mask for device type phy.
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- * Having different masks for host and device type phy helps
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- * in setting independent masks in case of SoCs like S5PV210,
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- * in which PHY0 and PHY1 enable bits belong to same register
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- * placed at position 0 and 1 respectively.
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- * Although for newer SoCs like exynos these bits belong to
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- * different registers altogether placed at position 0.
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- */
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-struct samsung_usbphy_drvdata {
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- int cpu_type;
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- int devphy_en_mask;
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- int hostphy_en_mask;
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- u32 devphy_reg_offset;
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- u32 hostphy_reg_offset;
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-};
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-
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-/*
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- * struct samsung_usbphy - transceiver driver state
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- * @phy: transceiver structure
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- * @plat: platform data
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- * @dev: The parent device supplied to the probe function
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- * @clk: usb phy clock
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- * @regs: usb phy controller registers memory base
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- * @pmuregs: USB device PHY_CONTROL register memory base
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- * @sysreg: USB2.0 PHY_CFG register memory base
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- * @ref_clk_freq: reference clock frequency selection
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- * @drv_data: driver data available for different SoCs
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- * @phy_type: Samsung SoCs specific phy types: #HOST
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- * #DEVICE
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- * @phy_usage: usage count for phy
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- * @lock: lock for phy operations
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- */
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-struct samsung_usbphy {
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- struct usb_phy phy;
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- struct samsung_usbphy_data *plat;
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- struct device *dev;
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- struct clk *clk;
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- void __iomem *regs;
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- void __iomem *pmuregs;
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- void __iomem *sysreg;
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- int ref_clk_freq;
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- const struct samsung_usbphy_drvdata *drv_data;
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- enum samsung_usb_phy_type phy_type;
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- atomic_t phy_usage;
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- spinlock_t lock;
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-};
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-
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-#define phy_to_sphy(x) container_of((x), struct samsung_usbphy, phy)
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-
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-int samsung_usbphy_set_host(struct usb_otg *otg, struct usb_bus *host)
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-{
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- if (!otg)
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- return -ENODEV;
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-
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- if (!otg->host)
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- otg->host = host;
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-
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- return 0;
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-}
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-
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-static int samsung_usbphy_parse_dt(struct samsung_usbphy *sphy)
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+int samsung_usbphy_parse_dt(struct samsung_usbphy *sphy)
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{
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struct device_node *usbphy_sys;
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@@ -282,13 +66,14 @@ err0:
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of_node_put(usbphy_sys);
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return -ENXIO;
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}
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+EXPORT_SYMBOL_GPL(samsung_usbphy_parse_dt);
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/*
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* Set isolation here for phy.
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* Here 'on = true' would mean USB PHY block is isolated, hence
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* de-activated and vice-versa.
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*/
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-static void samsung_usbphy_set_isolation(struct samsung_usbphy *sphy, bool on)
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+void samsung_usbphy_set_isolation(struct samsung_usbphy *sphy, bool on)
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{
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void __iomem *reg = NULL;
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u32 reg_val;
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@@ -336,11 +121,12 @@ static void samsung_usbphy_set_isolation(struct samsung_usbphy *sphy, bool on)
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writel(reg_val, reg);
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}
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+EXPORT_SYMBOL_GPL(samsung_usbphy_set_isolation);
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/*
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* Configure the mode of working of usb-phy here: HOST/DEVICE.
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*/
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-static void samsung_usbphy_cfg_sel(struct samsung_usbphy *sphy)
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+void samsung_usbphy_cfg_sel(struct samsung_usbphy *sphy)
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{
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u32 reg;
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@@ -358,13 +144,14 @@ static void samsung_usbphy_cfg_sel(struct samsung_usbphy *sphy)
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writel(reg, sphy->sysreg);
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}
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+EXPORT_SYMBOL_GPL(samsung_usbphy_cfg_sel);
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/*
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* PHYs are different for USB Device and USB Host.
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* This make sure that correct PHY type is selected before
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* any operation on PHY.
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*/
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-static int samsung_usbphy_set_type(struct usb_phy *phy,
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+int samsung_usbphy_set_type(struct usb_phy *phy,
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enum samsung_usb_phy_type phy_type)
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{
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struct samsung_usbphy *sphy = phy_to_sphy(phy);
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@@ -373,11 +160,12 @@ static int samsung_usbphy_set_type(struct usb_phy *phy,
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return 0;
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}
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+EXPORT_SYMBOL_GPL(samsung_usbphy_set_type);
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/*
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* Returns reference clock frequency selection value
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*/
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-static int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
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+int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
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{
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struct clk *ref_clk;
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int refclk_freq = 0;
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@@ -387,9 +175,9 @@ static int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
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* external crystal clock XXTI
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*/
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if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
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- ref_clk = clk_get(sphy->dev, "ext_xtal");
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+ ref_clk = devm_clk_get(sphy->dev, "ext_xtal");
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else
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- ref_clk = clk_get(sphy->dev, "xusbxti");
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+ ref_clk = devm_clk_get(sphy->dev, "xusbxti");
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if (IS_ERR(ref_clk)) {
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dev_err(sphy->dev, "Failed to get reference clock\n");
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return PTR_ERR(ref_clk);
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@@ -445,484 +233,4 @@ static int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
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return refclk_freq;
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}
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-
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-static bool exynos5_phyhost_is_on(void *regs)
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-{
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- u32 reg;
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-
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- reg = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
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-
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- return !(reg & HOST_CTRL0_SIDDQ);
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-}
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-
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-static void samsung_exynos5_usbphy_enable(struct samsung_usbphy *sphy)
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-{
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- void __iomem *regs = sphy->regs;
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- u32 phyclk = sphy->ref_clk_freq;
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- u32 phyhost;
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- u32 phyotg;
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- u32 phyhsic;
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- u32 ehcictrl;
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- u32 ohcictrl;
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-
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- /*
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- * phy_usage helps in keeping usage count for phy
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- * so that the first consumer enabling the phy is also
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- * the last consumer to disable it.
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- */
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-
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- atomic_inc(&sphy->phy_usage);
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-
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- if (exynos5_phyhost_is_on(regs)) {
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- dev_info(sphy->dev, "Already power on PHY\n");
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- return;
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- }
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-
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- /* Host configuration */
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- phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
|
|
|
-
|
|
|
- /* phy reference clock configuration */
|
|
|
- phyhost &= ~HOST_CTRL0_FSEL_MASK;
|
|
|
- phyhost |= HOST_CTRL0_FSEL(phyclk);
|
|
|
-
|
|
|
- /* host phy reset */
|
|
|
- phyhost &= ~(HOST_CTRL0_PHYSWRST |
|
|
|
- HOST_CTRL0_PHYSWRSTALL |
|
|
|
- HOST_CTRL0_SIDDQ |
|
|
|
- /* Enable normal mode of operation */
|
|
|
- HOST_CTRL0_FORCESUSPEND |
|
|
|
- HOST_CTRL0_FORCESLEEP);
|
|
|
-
|
|
|
- /* Link reset */
|
|
|
- phyhost |= (HOST_CTRL0_LINKSWRST |
|
|
|
- HOST_CTRL0_UTMISWRST |
|
|
|
- /* COMMON Block configuration during suspend */
|
|
|
- HOST_CTRL0_COMMONON_N);
|
|
|
- writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
|
|
|
- udelay(10);
|
|
|
- phyhost &= ~(HOST_CTRL0_LINKSWRST |
|
|
|
- HOST_CTRL0_UTMISWRST);
|
|
|
- writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
|
|
|
-
|
|
|
- /* OTG configuration */
|
|
|
- phyotg = readl(regs + EXYNOS5_PHY_OTG_SYS);
|
|
|
-
|
|
|
- /* phy reference clock configuration */
|
|
|
- phyotg &= ~OTG_SYS_FSEL_MASK;
|
|
|
- phyotg |= OTG_SYS_FSEL(phyclk);
|
|
|
-
|
|
|
- /* Enable normal mode of operation */
|
|
|
- phyotg &= ~(OTG_SYS_FORCESUSPEND |
|
|
|
- OTG_SYS_SIDDQ_UOTG |
|
|
|
- OTG_SYS_FORCESLEEP |
|
|
|
- OTG_SYS_REFCLKSEL_MASK |
|
|
|
- /* COMMON Block configuration during suspend */
|
|
|
- OTG_SYS_COMMON_ON);
|
|
|
-
|
|
|
- /* OTG phy & link reset */
|
|
|
- phyotg |= (OTG_SYS_PHY0_SWRST |
|
|
|
- OTG_SYS_LINKSWRST_UOTG |
|
|
|
- OTG_SYS_PHYLINK_SWRESET |
|
|
|
- OTG_SYS_OTGDISABLE |
|
|
|
- /* Set phy refclk */
|
|
|
- OTG_SYS_REFCLKSEL_CLKCORE);
|
|
|
-
|
|
|
- writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS);
|
|
|
- udelay(10);
|
|
|
- phyotg &= ~(OTG_SYS_PHY0_SWRST |
|
|
|
- OTG_SYS_LINKSWRST_UOTG |
|
|
|
- OTG_SYS_PHYLINK_SWRESET);
|
|
|
- writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS);
|
|
|
-
|
|
|
- /* HSIC phy configuration */
|
|
|
- phyhsic = (HSIC_CTRL_REFCLKDIV_12 |
|
|
|
- HSIC_CTRL_REFCLKSEL |
|
|
|
- HSIC_CTRL_PHYSWRST);
|
|
|
- writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1);
|
|
|
- writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2);
|
|
|
- udelay(10);
|
|
|
- phyhsic &= ~HSIC_CTRL_PHYSWRST;
|
|
|
- writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1);
|
|
|
- writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2);
|
|
|
-
|
|
|
- udelay(80);
|
|
|
-
|
|
|
- /* enable EHCI DMA burst */
|
|
|
- ehcictrl = readl(regs + EXYNOS5_PHY_HOST_EHCICTRL);
|
|
|
- ehcictrl |= (HOST_EHCICTRL_ENAINCRXALIGN |
|
|
|
- HOST_EHCICTRL_ENAINCR4 |
|
|
|
- HOST_EHCICTRL_ENAINCR8 |
|
|
|
- HOST_EHCICTRL_ENAINCR16);
|
|
|
- writel(ehcictrl, regs + EXYNOS5_PHY_HOST_EHCICTRL);
|
|
|
-
|
|
|
- /* set ohci_suspend_on_n */
|
|
|
- ohcictrl = readl(regs + EXYNOS5_PHY_HOST_OHCICTRL);
|
|
|
- ohcictrl |= HOST_OHCICTRL_SUSPLGCY;
|
|
|
- writel(ohcictrl, regs + EXYNOS5_PHY_HOST_OHCICTRL);
|
|
|
-}
|
|
|
-
|
|
|
-static void samsung_usbphy_enable(struct samsung_usbphy *sphy)
|
|
|
-{
|
|
|
- void __iomem *regs = sphy->regs;
|
|
|
- u32 phypwr;
|
|
|
- u32 phyclk;
|
|
|
- u32 rstcon;
|
|
|
-
|
|
|
- /* set clock frequency for PLL */
|
|
|
- phyclk = sphy->ref_clk_freq;
|
|
|
- phypwr = readl(regs + SAMSUNG_PHYPWR);
|
|
|
- rstcon = readl(regs + SAMSUNG_RSTCON);
|
|
|
-
|
|
|
- switch (sphy->drv_data->cpu_type) {
|
|
|
- case TYPE_S3C64XX:
|
|
|
- phyclk &= ~PHYCLK_COMMON_ON_N;
|
|
|
- phypwr &= ~PHYPWR_NORMAL_MASK;
|
|
|
- rstcon |= RSTCON_SWRST;
|
|
|
- break;
|
|
|
- case TYPE_EXYNOS4210:
|
|
|
- phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
|
|
|
- rstcon |= RSTCON_SWRST;
|
|
|
- default:
|
|
|
- break;
|
|
|
- }
|
|
|
-
|
|
|
- writel(phyclk, regs + SAMSUNG_PHYCLK);
|
|
|
- /* Configure PHY0 for normal operation*/
|
|
|
- writel(phypwr, regs + SAMSUNG_PHYPWR);
|
|
|
- /* reset all ports of PHY and Link */
|
|
|
- writel(rstcon, regs + SAMSUNG_RSTCON);
|
|
|
- udelay(10);
|
|
|
- rstcon &= ~RSTCON_SWRST;
|
|
|
- writel(rstcon, regs + SAMSUNG_RSTCON);
|
|
|
-}
|
|
|
-
|
|
|
-static void samsung_exynos5_usbphy_disable(struct samsung_usbphy *sphy)
|
|
|
-{
|
|
|
- void __iomem *regs = sphy->regs;
|
|
|
- u32 phyhost;
|
|
|
- u32 phyotg;
|
|
|
- u32 phyhsic;
|
|
|
-
|
|
|
- if (atomic_dec_return(&sphy->phy_usage) > 0) {
|
|
|
- dev_info(sphy->dev, "still being used\n");
|
|
|
- return;
|
|
|
- }
|
|
|
-
|
|
|
- phyhsic = (HSIC_CTRL_REFCLKDIV_12 |
|
|
|
- HSIC_CTRL_REFCLKSEL |
|
|
|
- HSIC_CTRL_SIDDQ |
|
|
|
- HSIC_CTRL_FORCESLEEP |
|
|
|
- HSIC_CTRL_FORCESUSPEND);
|
|
|
- writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1);
|
|
|
- writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2);
|
|
|
-
|
|
|
- phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
|
|
|
- phyhost |= (HOST_CTRL0_SIDDQ |
|
|
|
- HOST_CTRL0_FORCESUSPEND |
|
|
|
- HOST_CTRL0_FORCESLEEP |
|
|
|
- HOST_CTRL0_PHYSWRST |
|
|
|
- HOST_CTRL0_PHYSWRSTALL);
|
|
|
- writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
|
|
|
-
|
|
|
- phyotg = readl(regs + EXYNOS5_PHY_OTG_SYS);
|
|
|
- phyotg |= (OTG_SYS_FORCESUSPEND |
|
|
|
- OTG_SYS_SIDDQ_UOTG |
|
|
|
- OTG_SYS_FORCESLEEP);
|
|
|
- writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS);
|
|
|
-}
|
|
|
-
|
|
|
-static void samsung_usbphy_disable(struct samsung_usbphy *sphy)
|
|
|
-{
|
|
|
- void __iomem *regs = sphy->regs;
|
|
|
- u32 phypwr;
|
|
|
-
|
|
|
- phypwr = readl(regs + SAMSUNG_PHYPWR);
|
|
|
-
|
|
|
- switch (sphy->drv_data->cpu_type) {
|
|
|
- case TYPE_S3C64XX:
|
|
|
- phypwr |= PHYPWR_NORMAL_MASK;
|
|
|
- break;
|
|
|
- case TYPE_EXYNOS4210:
|
|
|
- phypwr |= PHYPWR_NORMAL_MASK_PHY0;
|
|
|
- default:
|
|
|
- break;
|
|
|
- }
|
|
|
-
|
|
|
- /* Disable analog and otg block power */
|
|
|
- writel(phypwr, regs + SAMSUNG_PHYPWR);
|
|
|
-}
|
|
|
-
|
|
|
-/*
|
|
|
- * The function passed to the usb driver for phy initialization
|
|
|
- */
|
|
|
-static int samsung_usbphy_init(struct usb_phy *phy)
|
|
|
-{
|
|
|
- struct samsung_usbphy *sphy;
|
|
|
- struct usb_bus *host = NULL;
|
|
|
- unsigned long flags;
|
|
|
- int ret = 0;
|
|
|
-
|
|
|
- sphy = phy_to_sphy(phy);
|
|
|
-
|
|
|
- host = phy->otg->host;
|
|
|
-
|
|
|
- /* Enable the phy clock */
|
|
|
- ret = clk_prepare_enable(sphy->clk);
|
|
|
- if (ret) {
|
|
|
- dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
|
|
|
- return ret;
|
|
|
- }
|
|
|
-
|
|
|
- spin_lock_irqsave(&sphy->lock, flags);
|
|
|
-
|
|
|
- if (host) {
|
|
|
- /* setting default phy-type for USB 2.0 */
|
|
|
- if (!strstr(dev_name(host->controller), "ehci") ||
|
|
|
- !strstr(dev_name(host->controller), "ohci"))
|
|
|
- samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_HOST);
|
|
|
- } else {
|
|
|
- samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
|
|
|
- }
|
|
|
-
|
|
|
- /* Disable phy isolation */
|
|
|
- if (sphy->plat && sphy->plat->pmu_isolation)
|
|
|
- sphy->plat->pmu_isolation(false);
|
|
|
- else
|
|
|
- samsung_usbphy_set_isolation(sphy, false);
|
|
|
-
|
|
|
- /* Selecting Host/OTG mode; After reset USB2.0PHY_CFG: HOST */
|
|
|
- samsung_usbphy_cfg_sel(sphy);
|
|
|
-
|
|
|
- /* Initialize usb phy registers */
|
|
|
- if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
|
|
|
- samsung_exynos5_usbphy_enable(sphy);
|
|
|
- else
|
|
|
- samsung_usbphy_enable(sphy);
|
|
|
-
|
|
|
- spin_unlock_irqrestore(&sphy->lock, flags);
|
|
|
-
|
|
|
- /* Disable the phy clock */
|
|
|
- clk_disable_unprepare(sphy->clk);
|
|
|
-
|
|
|
- return ret;
|
|
|
-}
|
|
|
-
|
|
|
-/*
|
|
|
- * The function passed to the usb driver for phy shutdown
|
|
|
- */
|
|
|
-static void samsung_usbphy_shutdown(struct usb_phy *phy)
|
|
|
-{
|
|
|
- struct samsung_usbphy *sphy;
|
|
|
- struct usb_bus *host = NULL;
|
|
|
- unsigned long flags;
|
|
|
-
|
|
|
- sphy = phy_to_sphy(phy);
|
|
|
-
|
|
|
- host = phy->otg->host;
|
|
|
-
|
|
|
- if (clk_prepare_enable(sphy->clk)) {
|
|
|
- dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
|
|
|
- return;
|
|
|
- }
|
|
|
-
|
|
|
- spin_lock_irqsave(&sphy->lock, flags);
|
|
|
-
|
|
|
- if (host) {
|
|
|
- /* setting default phy-type for USB 2.0 */
|
|
|
- if (!strstr(dev_name(host->controller), "ehci") ||
|
|
|
- !strstr(dev_name(host->controller), "ohci"))
|
|
|
- samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_HOST);
|
|
|
- } else {
|
|
|
- samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
|
|
|
- }
|
|
|
-
|
|
|
- /* De-initialize usb phy registers */
|
|
|
- if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
|
|
|
- samsung_exynos5_usbphy_disable(sphy);
|
|
|
- else
|
|
|
- samsung_usbphy_disable(sphy);
|
|
|
-
|
|
|
- /* Enable phy isolation */
|
|
|
- if (sphy->plat && sphy->plat->pmu_isolation)
|
|
|
- sphy->plat->pmu_isolation(true);
|
|
|
- else
|
|
|
- samsung_usbphy_set_isolation(sphy, true);
|
|
|
-
|
|
|
- spin_unlock_irqrestore(&sphy->lock, flags);
|
|
|
-
|
|
|
- clk_disable_unprepare(sphy->clk);
|
|
|
-}
|
|
|
-
|
|
|
-static const struct of_device_id samsung_usbphy_dt_match[];
|
|
|
-
|
|
|
-static inline const struct samsung_usbphy_drvdata
|
|
|
-*samsung_usbphy_get_driver_data(struct platform_device *pdev)
|
|
|
-{
|
|
|
- if (pdev->dev.of_node) {
|
|
|
- const struct of_device_id *match;
|
|
|
- match = of_match_node(samsung_usbphy_dt_match,
|
|
|
- pdev->dev.of_node);
|
|
|
- return match->data;
|
|
|
- }
|
|
|
-
|
|
|
- return (struct samsung_usbphy_drvdata *)
|
|
|
- platform_get_device_id(pdev)->driver_data;
|
|
|
-}
|
|
|
-
|
|
|
-static int samsung_usbphy_probe(struct platform_device *pdev)
|
|
|
-{
|
|
|
- struct samsung_usbphy *sphy;
|
|
|
- struct usb_otg *otg;
|
|
|
- struct samsung_usbphy_data *pdata = pdev->dev.platform_data;
|
|
|
- const struct samsung_usbphy_drvdata *drv_data;
|
|
|
- struct device *dev = &pdev->dev;
|
|
|
- struct resource *phy_mem;
|
|
|
- void __iomem *phy_base;
|
|
|
- struct clk *clk;
|
|
|
- int ret;
|
|
|
-
|
|
|
- phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
- if (!phy_mem) {
|
|
|
- dev_err(dev, "%s: missing mem resource\n", __func__);
|
|
|
- return -ENODEV;
|
|
|
- }
|
|
|
-
|
|
|
- phy_base = devm_ioremap_resource(dev, phy_mem);
|
|
|
- if (IS_ERR(phy_base))
|
|
|
- return PTR_ERR(phy_base);
|
|
|
-
|
|
|
- sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
|
|
|
- if (!sphy)
|
|
|
- return -ENOMEM;
|
|
|
-
|
|
|
- otg = devm_kzalloc(dev, sizeof(*otg), GFP_KERNEL);
|
|
|
- if (!otg)
|
|
|
- return -ENOMEM;
|
|
|
-
|
|
|
- drv_data = samsung_usbphy_get_driver_data(pdev);
|
|
|
-
|
|
|
- if (drv_data->cpu_type == TYPE_EXYNOS5250)
|
|
|
- clk = devm_clk_get(dev, "usbhost");
|
|
|
- else
|
|
|
- clk = devm_clk_get(dev, "otg");
|
|
|
-
|
|
|
- if (IS_ERR(clk)) {
|
|
|
- dev_err(dev, "Failed to get otg clock\n");
|
|
|
- return PTR_ERR(clk);
|
|
|
- }
|
|
|
-
|
|
|
- sphy->dev = dev;
|
|
|
-
|
|
|
- if (dev->of_node) {
|
|
|
- ret = samsung_usbphy_parse_dt(sphy);
|
|
|
- if (ret < 0)
|
|
|
- return ret;
|
|
|
- } else {
|
|
|
- if (!pdata) {
|
|
|
- dev_err(dev, "no platform data specified\n");
|
|
|
- return -EINVAL;
|
|
|
- }
|
|
|
- }
|
|
|
-
|
|
|
- sphy->plat = pdata;
|
|
|
- sphy->regs = phy_base;
|
|
|
- sphy->clk = clk;
|
|
|
- sphy->drv_data = drv_data;
|
|
|
- sphy->phy.dev = sphy->dev;
|
|
|
- sphy->phy.label = "samsung-usbphy";
|
|
|
- sphy->phy.init = samsung_usbphy_init;
|
|
|
- sphy->phy.shutdown = samsung_usbphy_shutdown;
|
|
|
- sphy->ref_clk_freq = samsung_usbphy_get_refclk_freq(sphy);
|
|
|
-
|
|
|
- sphy->phy.otg = otg;
|
|
|
- sphy->phy.otg->phy = &sphy->phy;
|
|
|
- sphy->phy.otg->set_host = samsung_usbphy_set_host;
|
|
|
-
|
|
|
- spin_lock_init(&sphy->lock);
|
|
|
-
|
|
|
- platform_set_drvdata(pdev, sphy);
|
|
|
-
|
|
|
- return usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB2);
|
|
|
-}
|
|
|
-
|
|
|
-static int samsung_usbphy_remove(struct platform_device *pdev)
|
|
|
-{
|
|
|
- struct samsung_usbphy *sphy = platform_get_drvdata(pdev);
|
|
|
-
|
|
|
- usb_remove_phy(&sphy->phy);
|
|
|
-
|
|
|
- if (sphy->pmuregs)
|
|
|
- iounmap(sphy->pmuregs);
|
|
|
- if (sphy->sysreg)
|
|
|
- iounmap(sphy->sysreg);
|
|
|
-
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-static const struct samsung_usbphy_drvdata usbphy_s3c64xx = {
|
|
|
- .cpu_type = TYPE_S3C64XX,
|
|
|
- .devphy_en_mask = S3C64XX_USBPHY_ENABLE,
|
|
|
-};
|
|
|
-
|
|
|
-static const struct samsung_usbphy_drvdata usbphy_exynos4 = {
|
|
|
- .cpu_type = TYPE_EXYNOS4210,
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- .devphy_en_mask = EXYNOS_USBPHY_ENABLE,
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- .hostphy_en_mask = EXYNOS_USBPHY_ENABLE,
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-};
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-
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-static struct samsung_usbphy_drvdata usbphy_exynos5 = {
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- .cpu_type = TYPE_EXYNOS5250,
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- .hostphy_en_mask = EXYNOS_USBPHY_ENABLE,
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- .hostphy_reg_offset = EXYNOS_USBHOST_PHY_CTRL_OFFSET,
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-};
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-
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-#ifdef CONFIG_OF
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-static const struct of_device_id samsung_usbphy_dt_match[] = {
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- {
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- .compatible = "samsung,s3c64xx-usbphy",
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- .data = &usbphy_s3c64xx,
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|
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- }, {
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|
- .compatible = "samsung,exynos4210-usbphy",
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- .data = &usbphy_exynos4,
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|
|
- }, {
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|
- .compatible = "samsung,exynos5250-usbphy",
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|
|
- .data = &usbphy_exynos5
|
|
|
- },
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|
|
- {},
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|
|
-};
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|
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-MODULE_DEVICE_TABLE(of, samsung_usbphy_dt_match);
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|
|
-#endif
|
|
|
-
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|
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-static struct platform_device_id samsung_usbphy_driver_ids[] = {
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|
|
- {
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|
|
- .name = "s3c64xx-usbphy",
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|
|
- .driver_data = (unsigned long)&usbphy_s3c64xx,
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|
|
- }, {
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|
|
- .name = "exynos4210-usbphy",
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|
|
- .driver_data = (unsigned long)&usbphy_exynos4,
|
|
|
- }, {
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|
|
- .name = "exynos5250-usbphy",
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|
|
- .driver_data = (unsigned long)&usbphy_exynos5,
|
|
|
- },
|
|
|
- {},
|
|
|
-};
|
|
|
-
|
|
|
-MODULE_DEVICE_TABLE(platform, samsung_usbphy_driver_ids);
|
|
|
-
|
|
|
-static struct platform_driver samsung_usbphy_driver = {
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|
|
- .probe = samsung_usbphy_probe,
|
|
|
- .remove = samsung_usbphy_remove,
|
|
|
- .id_table = samsung_usbphy_driver_ids,
|
|
|
- .driver = {
|
|
|
- .name = "samsung-usbphy",
|
|
|
- .owner = THIS_MODULE,
|
|
|
- .of_match_table = of_match_ptr(samsung_usbphy_dt_match),
|
|
|
- },
|
|
|
-};
|
|
|
-
|
|
|
-module_platform_driver(samsung_usbphy_driver);
|
|
|
-
|
|
|
-MODULE_DESCRIPTION("Samsung USB phy controller");
|
|
|
-MODULE_AUTHOR("Praveen Paneri <p.paneri@samsung.com>");
|
|
|
-MODULE_LICENSE("GPL");
|
|
|
-MODULE_ALIAS("platform:samsung-usbphy");
|
|
|
+EXPORT_SYMBOL_GPL(samsung_usbphy_get_refclk_freq);
|