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@@ -0,0 +1,533 @@
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+/*
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+ * CCI cache coherent interconnect driver
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+ *
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+ * Copyright (C) 2013 ARM Ltd.
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+ * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
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+ * kind, whether express or implied; without even the implied warranty
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+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/arm-cci.h>
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+#include <linux/io.h>
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+#include <linux/module.h>
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+#include <linux/of_address.h>
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+#include <linux/slab.h>
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+
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+#include <asm/cacheflush.h>
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+#include <asm/smp_plat.h>
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+
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+#define CCI_PORT_CTRL 0x0
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+#define CCI_CTRL_STATUS 0xc
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+
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+#define CCI_ENABLE_SNOOP_REQ 0x1
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+#define CCI_ENABLE_DVM_REQ 0x2
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+#define CCI_ENABLE_REQ (CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
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+
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+struct cci_nb_ports {
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+ unsigned int nb_ace;
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+ unsigned int nb_ace_lite;
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+};
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+
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+enum cci_ace_port_type {
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+ ACE_INVALID_PORT = 0x0,
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+ ACE_PORT,
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+ ACE_LITE_PORT,
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+};
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+
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+struct cci_ace_port {
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+ void __iomem *base;
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+ unsigned long phys;
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+ enum cci_ace_port_type type;
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+ struct device_node *dn;
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+};
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+
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+static struct cci_ace_port *ports;
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+static unsigned int nb_cci_ports;
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+
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+static void __iomem *cci_ctrl_base;
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+static unsigned long cci_ctrl_phys;
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+
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+struct cpu_port {
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+ u64 mpidr;
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+ u32 port;
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+};
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+
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+/*
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+ * Use the port MSB as valid flag, shift can be made dynamic
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+ * by computing number of bits required for port indexes.
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+ * Code disabling CCI cpu ports runs with D-cache invalidated
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+ * and SCTLR bit clear so data accesses must be kept to a minimum
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+ * to improve performance; for now shift is left static to
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+ * avoid one more data access while disabling the CCI port.
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+ */
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+#define PORT_VALID_SHIFT 31
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+#define PORT_VALID (0x1 << PORT_VALID_SHIFT)
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+
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+static inline void init_cpu_port(struct cpu_port *port, u32 index, u64 mpidr)
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+{
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+ port->port = PORT_VALID | index;
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+ port->mpidr = mpidr;
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+}
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+
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+static inline bool cpu_port_is_valid(struct cpu_port *port)
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+{
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+ return !!(port->port & PORT_VALID);
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+}
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+
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+static inline bool cpu_port_match(struct cpu_port *port, u64 mpidr)
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+{
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+ return port->mpidr == (mpidr & MPIDR_HWID_BITMASK);
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+}
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+
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+static struct cpu_port cpu_port[NR_CPUS];
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+
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+/**
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+ * __cci_ace_get_port - Function to retrieve the port index connected to
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+ * a cpu or device.
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+ *
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+ * @dn: device node of the device to look-up
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+ * @type: port type
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+ *
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+ * Return value:
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+ * - CCI port index if success
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+ * - -ENODEV if failure
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+ */
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+static int __cci_ace_get_port(struct device_node *dn, int type)
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+{
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+ int i;
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+ bool ace_match;
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+ struct device_node *cci_portn;
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+
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+ cci_portn = of_parse_phandle(dn, "cci-control-port", 0);
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+ for (i = 0; i < nb_cci_ports; i++) {
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+ ace_match = ports[i].type == type;
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+ if (ace_match && cci_portn == ports[i].dn)
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+ return i;
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+ }
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+ return -ENODEV;
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+}
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+
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+int cci_ace_get_port(struct device_node *dn)
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+{
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+ return __cci_ace_get_port(dn, ACE_LITE_PORT);
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+}
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+EXPORT_SYMBOL_GPL(cci_ace_get_port);
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+
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+static void __init cci_ace_init_ports(void)
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+{
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+ int port, ac, cpu;
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+ u64 hwid;
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+ const u32 *cell;
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+ struct device_node *cpun, *cpus;
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+
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+ cpus = of_find_node_by_path("/cpus");
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+ if (WARN(!cpus, "Missing cpus node, bailing out\n"))
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+ return;
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+
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+ if (WARN_ON(of_property_read_u32(cpus, "#address-cells", &ac)))
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+ ac = of_n_addr_cells(cpus);
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+
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+ /*
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+ * Port index look-up speeds up the function disabling ports by CPU,
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+ * since the logical to port index mapping is done once and does
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+ * not change after system boot.
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+ * The stashed index array is initialized for all possible CPUs
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+ * at probe time.
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+ */
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+ for_each_child_of_node(cpus, cpun) {
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+ if (of_node_cmp(cpun->type, "cpu"))
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+ continue;
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+ cell = of_get_property(cpun, "reg", NULL);
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+ if (WARN(!cell, "%s: missing reg property\n", cpun->full_name))
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+ continue;
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+
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+ hwid = of_read_number(cell, ac);
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+ cpu = get_logical_index(hwid & MPIDR_HWID_BITMASK);
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+
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+ if (cpu < 0 || !cpu_possible(cpu))
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+ continue;
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+ port = __cci_ace_get_port(cpun, ACE_PORT);
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+ if (port < 0)
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+ continue;
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+
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+ init_cpu_port(&cpu_port[cpu], port, cpu_logical_map(cpu));
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+ }
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+
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+ for_each_possible_cpu(cpu) {
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+ WARN(!cpu_port_is_valid(&cpu_port[cpu]),
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+ "CPU %u does not have an associated CCI port\n",
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+ cpu);
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+ }
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+}
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+/*
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+ * Functions to enable/disable a CCI interconnect slave port
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+ *
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+ * They are called by low-level power management code to disable slave
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+ * interfaces snoops and DVM broadcast.
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+ * Since they may execute with cache data allocation disabled and
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+ * after the caches have been cleaned and invalidated the functions provide
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+ * no explicit locking since they may run with D-cache disabled, so normal
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+ * cacheable kernel locks based on ldrex/strex may not work.
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+ * Locking has to be provided by BSP implementations to ensure proper
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+ * operations.
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+ */
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+
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+/**
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+ * cci_port_control() - function to control a CCI port
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+ *
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+ * @port: index of the port to setup
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+ * @enable: if true enables the port, if false disables it
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+ */
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+static void notrace cci_port_control(unsigned int port, bool enable)
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+{
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+ void __iomem *base = ports[port].base;
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+
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+ writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL);
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+ /*
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+ * This function is called from power down procedures
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+ * and must not execute any instruction that might
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+ * cause the processor to be put in a quiescent state
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+ * (eg wfi). Hence, cpu_relax() can not be added to this
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+ * read loop to optimize power, since it might hide possibly
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+ * disruptive operations.
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+ */
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+ while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1)
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+ ;
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+}
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+
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+/**
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+ * cci_disable_port_by_cpu() - function to disable a CCI port by CPU
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+ * reference
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+ *
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+ * @mpidr: mpidr of the CPU whose CCI port should be disabled
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+ *
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+ * Disabling a CCI port for a CPU implies disabling the CCI port
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+ * controlling that CPU cluster. Code disabling CPU CCI ports
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+ * must make sure that the CPU running the code is the last active CPU
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+ * in the cluster ie all other CPUs are quiescent in a low power state.
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+ *
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+ * Return:
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+ * 0 on success
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+ * -ENODEV on port look-up failure
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+ */
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+int notrace cci_disable_port_by_cpu(u64 mpidr)
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+{
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+ int cpu;
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+ bool is_valid;
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+ for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
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+ is_valid = cpu_port_is_valid(&cpu_port[cpu]);
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+ if (is_valid && cpu_port_match(&cpu_port[cpu], mpidr)) {
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+ cci_port_control(cpu_port[cpu].port, false);
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+ return 0;
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+ }
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+ }
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+ return -ENODEV;
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+}
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+EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu);
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+
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+/**
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+ * cci_enable_port_for_self() - enable a CCI port for calling CPU
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+ *
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+ * Enabling a CCI port for the calling CPU implies enabling the CCI
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+ * port controlling that CPU's cluster. Caller must make sure that the
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+ * CPU running the code is the first active CPU in the cluster and all
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+ * other CPUs are quiescent in a low power state or waiting for this CPU
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+ * to complete the CCI initialization.
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+ *
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+ * Because this is called when the MMU is still off and with no stack,
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+ * the code must be position independent and ideally rely on callee
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+ * clobbered registers only. To achieve this we must code this function
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+ * entirely in assembler.
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+ *
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+ * On success this returns with the proper CCI port enabled. In case of
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+ * any failure this never returns as the inability to enable the CCI is
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+ * fatal and there is no possible recovery at this stage.
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+ */
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+asmlinkage void __naked cci_enable_port_for_self(void)
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+{
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+ asm volatile ("\n"
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+
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+" mrc p15, 0, r0, c0, c0, 5 @ get MPIDR value \n"
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+" and r0, r0, #"__stringify(MPIDR_HWID_BITMASK)" \n"
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+" adr r1, 5f \n"
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+" ldr r2, [r1] \n"
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+" add r1, r1, r2 @ &cpu_port \n"
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+" add ip, r1, %[sizeof_cpu_port] \n"
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+
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+ /* Loop over the cpu_port array looking for a matching MPIDR */
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+"1: ldr r2, [r1, %[offsetof_cpu_port_mpidr_lsb]] \n"
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+" cmp r2, r0 @ compare MPIDR \n"
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+" bne 2f \n"
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+
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+ /* Found a match, now test port validity */
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+" ldr r3, [r1, %[offsetof_cpu_port_port]] \n"
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+" tst r3, #"__stringify(PORT_VALID)" \n"
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+" bne 3f \n"
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+
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+ /* no match, loop with the next cpu_port entry */
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+"2: add r1, r1, %[sizeof_struct_cpu_port] \n"
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+" cmp r1, ip @ done? \n"
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+" blo 1b \n"
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+
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+ /* CCI port not found -- cheaply try to stall this CPU */
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+"cci_port_not_found: \n"
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+" wfi \n"
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+" wfe \n"
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+" b cci_port_not_found \n"
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+
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+ /* Use matched port index to look up the corresponding ports entry */
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+"3: bic r3, r3, #"__stringify(PORT_VALID)" \n"
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+" adr r0, 6f \n"
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+" ldmia r0, {r1, r2} \n"
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+" sub r1, r1, r0 @ virt - phys \n"
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+" ldr r0, [r0, r2] @ *(&ports) \n"
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+" mov r2, %[sizeof_struct_ace_port] \n"
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+" mla r0, r2, r3, r0 @ &ports[index] \n"
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+" sub r0, r0, r1 @ virt_to_phys() \n"
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+
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+ /* Enable the CCI port */
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+" ldr r0, [r0, %[offsetof_port_phys]] \n"
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+" mov r3, #"__stringify(CCI_ENABLE_REQ)" \n"
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+" str r3, [r0, #"__stringify(CCI_PORT_CTRL)"] \n"
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+
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+ /* poll the status reg for completion */
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+" adr r1, 7f \n"
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+" ldr r0, [r1] \n"
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+" ldr r0, [r0, r1] @ cci_ctrl_base \n"
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+"4: ldr r1, [r0, #"__stringify(CCI_CTRL_STATUS)"] \n"
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+" tst r1, #1 \n"
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+" bne 4b \n"
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+
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+" mov r0, #0 \n"
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+" bx lr \n"
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+
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+" .align 2 \n"
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+"5: .word cpu_port - . \n"
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+"6: .word . \n"
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+" .word ports - 6b \n"
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+"7: .word cci_ctrl_phys - . \n"
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+ : :
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+ [sizeof_cpu_port] "i" (sizeof(cpu_port)),
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+#ifndef __ARMEB__
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+ [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)),
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+#else
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+ [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)+4),
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+#endif
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+ [offsetof_cpu_port_port] "i" (offsetof(struct cpu_port, port)),
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+ [sizeof_struct_cpu_port] "i" (sizeof(struct cpu_port)),
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+ [sizeof_struct_ace_port] "i" (sizeof(struct cci_ace_port)),
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+ [offsetof_port_phys] "i" (offsetof(struct cci_ace_port, phys)) );
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+
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+ unreachable();
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+}
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+
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+/**
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+ * __cci_control_port_by_device() - function to control a CCI port by device
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+ * reference
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+ *
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+ * @dn: device node pointer of the device whose CCI port should be
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+ * controlled
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+ * @enable: if true enables the port, if false disables it
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+ *
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+ * Return:
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+ * 0 on success
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+ * -ENODEV on port look-up failure
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+ */
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+int notrace __cci_control_port_by_device(struct device_node *dn, bool enable)
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+{
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+ int port;
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+
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+ if (!dn)
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+ return -ENODEV;
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+
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+ port = __cci_ace_get_port(dn, ACE_LITE_PORT);
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+ if (WARN_ONCE(port < 0, "node %s ACE lite port look-up failure\n",
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+ dn->full_name))
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+ return -ENODEV;
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+ cci_port_control(port, enable);
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(__cci_control_port_by_device);
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+
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+/**
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+ * __cci_control_port_by_index() - function to control a CCI port by port index
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+ *
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+ * @port: port index previously retrieved with cci_ace_get_port()
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+ * @enable: if true enables the port, if false disables it
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+ *
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+ * Return:
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+ * 0 on success
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+ * -ENODEV on port index out of range
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+ * -EPERM if operation carried out on an ACE PORT
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+ */
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+int notrace __cci_control_port_by_index(u32 port, bool enable)
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+{
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+ if (port >= nb_cci_ports || ports[port].type == ACE_INVALID_PORT)
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+ return -ENODEV;
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+ /*
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+ * CCI control for ports connected to CPUS is extremely fragile
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+ * and must be made to go through a specific and controlled
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+ * interface (ie cci_disable_port_by_cpu(); control by general purpose
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+ * indexing is therefore disabled for ACE ports.
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+ */
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+ if (ports[port].type == ACE_PORT)
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+ return -EPERM;
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+
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+ cci_port_control(port, enable);
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(__cci_control_port_by_index);
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+
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+static const struct cci_nb_ports cci400_ports = {
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+ .nb_ace = 2,
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+ .nb_ace_lite = 3
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+};
|
|
|
+
|
|
|
+static const struct of_device_id arm_cci_matches[] = {
|
|
|
+ {.compatible = "arm,cci-400", .data = &cci400_ports },
|
|
|
+ {},
|
|
|
+};
|
|
|
+
|
|
|
+static const struct of_device_id arm_cci_ctrl_if_matches[] = {
|
|
|
+ {.compatible = "arm,cci-400-ctrl-if", },
|
|
|
+ {},
|
|
|
+};
|
|
|
+
|
|
|
+static int __init cci_probe(void)
|
|
|
+{
|
|
|
+ struct cci_nb_ports const *cci_config;
|
|
|
+ int ret, i, nb_ace = 0, nb_ace_lite = 0;
|
|
|
+ struct device_node *np, *cp;
|
|
|
+ struct resource res;
|
|
|
+ const char *match_str;
|
|
|
+ bool is_ace;
|
|
|
+
|
|
|
+ np = of_find_matching_node(NULL, arm_cci_matches);
|
|
|
+ if (!np)
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ cci_config = of_match_node(arm_cci_matches, np)->data;
|
|
|
+ if (!cci_config)
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite;
|
|
|
+
|
|
|
+ ports = kcalloc(sizeof(*ports), nb_cci_ports, GFP_KERNEL);
|
|
|
+ if (!ports)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ ret = of_address_to_resource(np, 0, &res);
|
|
|
+ if (!ret) {
|
|
|
+ cci_ctrl_base = ioremap(res.start, resource_size(&res));
|
|
|
+ cci_ctrl_phys = res.start;
|
|
|
+ }
|
|
|
+ if (ret || !cci_ctrl_base) {
|
|
|
+ WARN(1, "unable to ioremap CCI ctrl\n");
|
|
|
+ ret = -ENXIO;
|
|
|
+ goto memalloc_err;
|
|
|
+ }
|
|
|
+
|
|
|
+ for_each_child_of_node(np, cp) {
|
|
|
+ if (!of_match_node(arm_cci_ctrl_if_matches, cp))
|
|
|
+ continue;
|
|
|
+
|
|
|
+ i = nb_ace + nb_ace_lite;
|
|
|
+
|
|
|
+ if (i >= nb_cci_ports)
|
|
|
+ break;
|
|
|
+
|
|
|
+ if (of_property_read_string(cp, "interface-type",
|
|
|
+ &match_str)) {
|
|
|
+ WARN(1, "node %s missing interface-type property\n",
|
|
|
+ cp->full_name);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+ is_ace = strcmp(match_str, "ace") == 0;
|
|
|
+ if (!is_ace && strcmp(match_str, "ace-lite")) {
|
|
|
+ WARN(1, "node %s containing invalid interface-type property, skipping it\n",
|
|
|
+ cp->full_name);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = of_address_to_resource(cp, 0, &res);
|
|
|
+ if (!ret) {
|
|
|
+ ports[i].base = ioremap(res.start, resource_size(&res));
|
|
|
+ ports[i].phys = res.start;
|
|
|
+ }
|
|
|
+ if (ret || !ports[i].base) {
|
|
|
+ WARN(1, "unable to ioremap CCI port %d\n", i);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (is_ace) {
|
|
|
+ if (WARN_ON(nb_ace >= cci_config->nb_ace))
|
|
|
+ continue;
|
|
|
+ ports[i].type = ACE_PORT;
|
|
|
+ ++nb_ace;
|
|
|
+ } else {
|
|
|
+ if (WARN_ON(nb_ace_lite >= cci_config->nb_ace_lite))
|
|
|
+ continue;
|
|
|
+ ports[i].type = ACE_LITE_PORT;
|
|
|
+ ++nb_ace_lite;
|
|
|
+ }
|
|
|
+ ports[i].dn = cp;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* initialize a stashed array of ACE ports to speed-up look-up */
|
|
|
+ cci_ace_init_ports();
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Multi-cluster systems may need this data when non-coherent, during
|
|
|
+ * cluster power-up/power-down. Make sure it reaches main memory.
|
|
|
+ */
|
|
|
+ sync_cache_w(&cci_ctrl_base);
|
|
|
+ sync_cache_w(&cci_ctrl_phys);
|
|
|
+ sync_cache_w(&ports);
|
|
|
+ sync_cache_w(&cpu_port);
|
|
|
+ __sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports);
|
|
|
+ pr_info("ARM CCI driver probed\n");
|
|
|
+ return 0;
|
|
|
+
|
|
|
+memalloc_err:
|
|
|
+
|
|
|
+ kfree(ports);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int cci_init_status = -EAGAIN;
|
|
|
+static DEFINE_MUTEX(cci_probing);
|
|
|
+
|
|
|
+static int __init cci_init(void)
|
|
|
+{
|
|
|
+ if (cci_init_status != -EAGAIN)
|
|
|
+ return cci_init_status;
|
|
|
+
|
|
|
+ mutex_lock(&cci_probing);
|
|
|
+ if (cci_init_status == -EAGAIN)
|
|
|
+ cci_init_status = cci_probe();
|
|
|
+ mutex_unlock(&cci_probing);
|
|
|
+ return cci_init_status;
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * To sort out early init calls ordering a helper function is provided to
|
|
|
+ * check if the CCI driver has beed initialized. Function check if the driver
|
|
|
+ * has been initialized, if not it calls the init function that probes
|
|
|
+ * the driver and updates the return value.
|
|
|
+ */
|
|
|
+bool __init cci_probed(void)
|
|
|
+{
|
|
|
+ return cci_init() == 0;
|
|
|
+}
|
|
|
+EXPORT_SYMBOL_GPL(cci_probed);
|
|
|
+
|
|
|
+early_initcall(cci_init);
|
|
|
+MODULE_LICENSE("GPL");
|
|
|
+MODULE_DESCRIPTION("ARM CCI support");
|
Olof Johansson