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@@ -641,11 +641,47 @@ static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
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static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
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{
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u32 reg1;
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+ u16 ctrl;
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+
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+ /* release GPHY Control reset */
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+ sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
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+
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+ /* release GMAC reset */
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+ sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
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+
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+ if (hw->flags & SKY2_HW_NEWER_PHY) {
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+ /* select page 2 to access MAC control register */
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+ gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
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+
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+ ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
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+ /* allow GMII Power Down */
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+ ctrl &= ~PHY_M_MAC_GMIF_PUP;
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+ gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
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+
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+ /* set page register back to 0 */
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+ gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
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+ }
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+
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+ /* setup General Purpose Control Register */
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+ gma_write16(hw, port, GM_GP_CTRL,
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+ GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
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+
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+ if (hw->chip_id != CHIP_ID_YUKON_EC) {
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+ if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
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+ ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
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+
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+ /* enable Power Down */
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+ ctrl |= PHY_M_PC_POW_D_ENA;
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+ gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
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+ }
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+
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+ /* set IEEE compatible Power Down Mode (dev. #4.99) */
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+ gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
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+ }
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
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reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
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- reg1 |= phy_power[port];
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-
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+ reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
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sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
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}
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