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@@ -39,14 +39,6 @@
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/* Primary Control Offset */
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#define IDE_PALM_ATA_PRI_CTL_OFFSET 0x3F6
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-/*
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- * PalmChip 3710 IDE Controller UDMA timing structure Definition
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- */
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-struct palm_bk3710_udmatiming {
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- unsigned int rptime; /* Ready to pause time */
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- unsigned int cycletime; /* Cycle Time */
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-};
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-
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#define BK3710_BMICP 0x00
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#define BK3710_BMISP 0x02
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#define BK3710_BMIDTP 0x04
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@@ -75,13 +67,19 @@ struct palm_bk3710_udmatiming {
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static unsigned ideclk_period; /* in nanoseconds */
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+struct palm_bk3710_udmatiming {
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+ unsigned int rptime; /* tRP -- Ready to pause time (nsec) */
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+ unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */
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+ /* tENV is always a minimum of 20 nsec */
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+};
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+
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static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = {
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- {160, 240}, /* UDMA Mode 0 */
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- {125, 160}, /* UDMA Mode 1 */
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- {100, 120}, /* UDMA Mode 2 */
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- {100, 90}, /* UDMA Mode 3 */
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- {100, 60}, /* UDMA Mode 4 */
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- {85, 40}, /* UDMA Mode 5 */
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+ {160, 240 / 2,}, /* UDMA Mode 0 */
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+ {125, 160 / 2,}, /* UDMA Mode 1 */
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+ {100, 120 / 2,}, /* UDMA Mode 2 */
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+ {100, 90 / 2,}, /* UDMA Mode 3 */
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+ {100, 60 / 2,}, /* UDMA Mode 4 */
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+ {85, 40 / 2,}, /* UDMA Mode 5 */
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};
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static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,
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