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@@ -39,42 +39,31 @@ EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
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*/
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/* transaction type */
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-const char *tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
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+const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
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EXPORT_SYMBOL_GPL(tt_msgs);
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/* cache level */
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-const char *ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
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+const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
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EXPORT_SYMBOL_GPL(ll_msgs);
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/* memory transaction type */
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-const char *rrrr_msgs[] = {
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+const char * const rrrr_msgs[] = {
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"GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
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};
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EXPORT_SYMBOL_GPL(rrrr_msgs);
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/* participating processor */
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-const char *pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
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+const char * const pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
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EXPORT_SYMBOL_GPL(pp_msgs);
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/* request timeout */
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-const char *to_msgs[] = { "no timeout", "timed out" };
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+const char * const to_msgs[] = { "no timeout", "timed out" };
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EXPORT_SYMBOL_GPL(to_msgs);
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/* memory or i/o */
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-const char *ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
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+const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
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EXPORT_SYMBOL_GPL(ii_msgs);
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-static const char *f10h_nb_mce_desc[] = {
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- "HT link data error",
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- "Protocol error (link, L3, probe filter, etc.)",
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- "Parity error in NB-internal arrays",
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- "Link Retry due to IO link transmission error",
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- "L3 ECC data cache error",
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- "ECC error in L3 cache tag",
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- "L3 LRU parity bits error",
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- "ECC Error in the Probe Filter directory"
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-};
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-
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static const char * const f15h_ic_mce_desc[] = {
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"UC during a demand linefill from L2",
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"Parity error during data load from IC",
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@@ -88,7 +77,7 @@ static const char * const f15h_ic_mce_desc[] = {
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"Parity error for IC probe tag valid bit",
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"PFB non-cacheable bit parity error",
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"PFB valid bit parity error", /* xec = 0xd */
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- "patch RAM", /* xec = 010 */
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+ "Microcode Patch Buffer", /* xec = 010 */
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"uop queue",
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"insn buffer",
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"predecode buffer",
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@@ -104,7 +93,7 @@ static const char * const f15h_cu_mce_desc[] = {
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"WCC Tag ECC error",
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"WCC Data ECC error",
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"WCB Data parity error",
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- "VB Data/ECC error",
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+ "VB Data ECC or parity error",
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"L2 Tag ECC error", /* xec = 0x10 */
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"Hard L2 Tag ECC error",
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"Multiple hits on L2 tag",
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@@ -112,6 +101,28 @@ static const char * const f15h_cu_mce_desc[] = {
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"PRB address parity error"
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};
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+static const char * const nb_mce_desc[] = {
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+ "DRAM ECC error detected on the NB",
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+ "CRC error detected on HT link",
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+ "Link-defined sync error packets detected on HT link",
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+ "HT Master abort",
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+ "HT Target abort",
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+ "Invalid GART PTE entry during GART table walk",
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+ "Unsupported atomic RMW received from an IO link",
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+ "Watchdog timeout due to lack of progress",
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+ "DRAM ECC error detected on the NB",
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+ "SVM DMA Exclusion Vector error",
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+ "HT data error detected on link",
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+ "Protocol error (link, L3, probe filter)",
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+ "NB internal arrays parity error",
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+ "DRAM addr/ctl signals parity error",
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+ "IO link transmission error",
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+ "L3 data cache ECC error", /* xec = 0x1c */
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+ "L3 cache tag error",
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+ "L3 LRU parity bits error",
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+ "ECC Error in the Probe Filter directory"
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+};
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+
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static const char * const fr_ex_mce_desc[] = {
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"CPU Watchdog timer expire",
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"Wakeup array dest tag",
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@@ -125,7 +136,7 @@ static const char * const fr_ex_mce_desc[] = {
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"Physical register file AG0 port",
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"Physical register file AG1 port",
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"Flag register file",
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- "DE correctable error could not be corrected"
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+ "DE error occurred"
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};
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static bool f12h_dc_mce(u16 ec, u8 xec)
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@@ -255,10 +266,9 @@ static bool f15h_dc_mce(u16 ec, u8 xec)
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} else if (BUS_ERROR(ec)) {
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if (!xec)
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- pr_cont("during system linefill.\n");
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+ pr_cont("System Read Data Error.\n");
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else
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- pr_cont(" Internal %s condition.\n",
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- ((xec == 1) ? "livelock" : "deadlock"));
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+ pr_cont(" Internal error condition type %d.\n", xec);
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} else
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ret = false;
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@@ -355,7 +365,11 @@ static bool f15h_ic_mce(u16 ec, u8 xec)
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pr_cont("%s.\n", f15h_ic_mce_desc[xec-2]);
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break;
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- case 0x10 ... 0x14:
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+ case 0x10:
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+ pr_cont("%s.\n", f15h_ic_mce_desc[xec-4]);
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+ break;
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+
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+ case 0x11 ... 0x14:
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pr_cont("Decoder %s parity error.\n", f15h_ic_mce_desc[xec-4]);
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break;
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@@ -496,58 +510,31 @@ wrong_ls_mce:
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pr_emerg(HW_ERR "Corrupted LS MCE info?\n");
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}
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-static bool k8_nb_mce(u16 ec, u8 xec)
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+void amd_decode_nb_mce(struct mce *m)
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{
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- bool ret = true;
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-
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- switch (xec) {
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- case 0x1:
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- pr_cont("CRC error detected on HT link.\n");
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- break;
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-
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- case 0x5:
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- pr_cont("Invalid GART PTE entry during GART table walk.\n");
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- break;
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-
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- case 0x6:
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- pr_cont("Unsupported atomic RMW received from an IO link.\n");
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- break;
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-
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- case 0x0:
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- case 0x8:
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- if (boot_cpu_data.x86 == 0x11)
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- return false;
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-
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- pr_cont("DRAM ECC error detected on the NB.\n");
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- break;
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-
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- case 0xd:
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- pr_cont("Parity error on the DRAM addr/ctl signals.\n");
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- break;
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-
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- default:
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- ret = false;
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- break;
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- }
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+ struct cpuinfo_x86 *c = &boot_cpu_data;
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+ int node_id = amd_get_nb_id(m->extcpu);
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+ u16 ec = EC(m->status);
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+ u8 xec = XEC(m->status, 0x1f);
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+ u8 offset = 0;
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- return ret;
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-}
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+ pr_emerg(HW_ERR "Northbridge Error (node %d): ", node_id);
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-static bool f10h_nb_mce(u16 ec, u8 xec)
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-{
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- bool ret = true;
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- u8 offset = 0;
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+ switch (xec) {
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+ case 0x0 ... 0xe:
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- if (k8_nb_mce(ec, xec))
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- return true;
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+ /* special handling for DRAM ECCs */
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+ if (xec == 0x0 || xec == 0x8) {
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+ /* no ECCs on F11h */
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+ if (c->x86 == 0x11)
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+ goto wrong_nb_mce;
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- switch(xec) {
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- case 0xa ... 0xc:
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- offset = 10;
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- break;
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+ pr_cont("%s.\n", nb_mce_desc[xec]);
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- case 0xe:
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- offset = 11;
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+ if (nb_bus_decoder)
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+ nb_bus_decoder(node_id, m);
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+ return;
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+ }
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break;
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case 0xf:
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@@ -556,83 +543,25 @@ static bool f10h_nb_mce(u16 ec, u8 xec)
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else if (BUS_ERROR(ec))
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pr_cont("DMA Exclusion Vector Table Walk error.\n");
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else
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- ret = false;
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-
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- goto out;
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- break;
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+ goto wrong_nb_mce;
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+ return;
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case 0x19:
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if (boot_cpu_data.x86 == 0x15)
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pr_cont("Compute Unit Data Error.\n");
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else
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- ret = false;
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-
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- goto out;
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- break;
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+ goto wrong_nb_mce;
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+ return;
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case 0x1c ... 0x1f:
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- offset = 24;
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+ offset = 13;
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break;
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default:
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- ret = false;
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-
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- goto out;
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- break;
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- }
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-
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- pr_cont("%s.\n", f10h_nb_mce_desc[xec - offset]);
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-
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-out:
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- return ret;
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-}
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-
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-static bool nb_noop_mce(u16 ec, u8 xec)
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-{
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- return false;
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-}
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-
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-void amd_decode_nb_mce(struct mce *m)
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-{
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- struct cpuinfo_x86 *c = &boot_cpu_data;
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- int node_id = amd_get_nb_id(m->extcpu);
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- u16 ec = EC(m->status);
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- u8 xec = XEC(m->status, 0x1f);
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-
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- pr_emerg(HW_ERR "Northbridge Error (node %d): ", node_id);
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-
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- switch (xec) {
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- case 0x2:
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- pr_cont("Sync error (sync packets on HT link detected).\n");
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- return;
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-
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- case 0x3:
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- pr_cont("HT Master abort.\n");
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- return;
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-
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- case 0x4:
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- pr_cont("HT Target abort.\n");
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- return;
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-
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- case 0x7:
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- pr_cont("NB Watchdog timeout.\n");
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- return;
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-
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- case 0x9:
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- pr_cont("SVM DMA Exclusion Vector error.\n");
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- return;
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-
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- default:
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- break;
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- }
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-
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- if (!fam_ops->nb_mce(ec, xec))
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goto wrong_nb_mce;
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+ }
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- if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x15)
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- if ((xec == 0x8 || xec == 0x0) && nb_bus_decoder)
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- nb_bus_decoder(node_id, m);
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-
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+ pr_cont("%s.\n", nb_mce_desc[xec - offset]);
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return;
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wrong_nb_mce:
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@@ -648,9 +577,6 @@ static void amd_decode_fr_mce(struct mce *m)
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if (c->x86 == 0xf || c->x86 == 0x11)
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goto wrong_fr_mce;
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- if (c->x86 != 0x15 && xec != 0x0)
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- goto wrong_fr_mce;
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-
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pr_emerg(HW_ERR "%s Error: ",
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(c->x86 == 0x15 ? "Execution Unit" : "FIROB"));
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@@ -841,39 +767,33 @@ static int __init mce_amd_init(void)
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case 0xf:
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fam_ops->dc_mce = k8_dc_mce;
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fam_ops->ic_mce = k8_ic_mce;
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- fam_ops->nb_mce = k8_nb_mce;
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break;
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case 0x10:
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fam_ops->dc_mce = f10h_dc_mce;
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fam_ops->ic_mce = k8_ic_mce;
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- fam_ops->nb_mce = f10h_nb_mce;
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break;
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case 0x11:
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fam_ops->dc_mce = k8_dc_mce;
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fam_ops->ic_mce = k8_ic_mce;
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- fam_ops->nb_mce = f10h_nb_mce;
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break;
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case 0x12:
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fam_ops->dc_mce = f12h_dc_mce;
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fam_ops->ic_mce = k8_ic_mce;
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- fam_ops->nb_mce = nb_noop_mce;
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break;
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case 0x14:
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nb_err_cpumask = 0x3;
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fam_ops->dc_mce = f14h_dc_mce;
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fam_ops->ic_mce = f14h_ic_mce;
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- fam_ops->nb_mce = nb_noop_mce;
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break;
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case 0x15:
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xec_mask = 0x1f;
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fam_ops->dc_mce = f15h_dc_mce;
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fam_ops->ic_mce = f15h_ic_mce;
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- fam_ops->nb_mce = f10h_nb_mce;
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break;
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default:
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Linus Torvalds