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@@ -24,39 +24,54 @@
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* transferred first, "BE" means that the most significant bits are transferred
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* first, and "PADHI" and "PADLO" define which bits - low or high, in the
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* incomplete high byte, are filled with padding bits.
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+ *
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+ * The pixel codes are grouped by type, bus_width, bits per component, samples
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+ * per pixel and order of subsamples. Numerical values are sorted using generic
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+ * numerical sort order (8 thus comes before 10).
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+ *
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+ * As their value can't change when a new pixel code is inserted in the
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+ * enumeration, the pixel codes are explicitly given a numerical value. The next
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+ * free values for each category are listed below, update them when inserting
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+ * new pixel codes.
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*/
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enum v4l2_mbus_pixelcode {
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- V4L2_MBUS_FMT_FIXED = 1,
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- V4L2_MBUS_FMT_YUYV8_2X8,
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- V4L2_MBUS_FMT_YVYU8_2X8,
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- V4L2_MBUS_FMT_UYVY8_2X8,
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- V4L2_MBUS_FMT_VYUY8_2X8,
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- V4L2_MBUS_FMT_YVYU10_2X10,
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- V4L2_MBUS_FMT_YUYV10_2X10,
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- V4L2_MBUS_FMT_YVYU10_1X20,
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- V4L2_MBUS_FMT_YUYV10_1X20,
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- V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE,
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- V4L2_MBUS_FMT_RGB444_2X8_PADHI_BE,
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- V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
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- V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE,
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- V4L2_MBUS_FMT_RGB565_2X8_LE,
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- V4L2_MBUS_FMT_RGB565_2X8_BE,
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- V4L2_MBUS_FMT_BGR565_2X8_LE,
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- V4L2_MBUS_FMT_BGR565_2X8_BE,
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- V4L2_MBUS_FMT_SBGGR8_1X8,
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- V4L2_MBUS_FMT_SBGGR10_1X10,
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- V4L2_MBUS_FMT_Y8_1X8,
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- V4L2_MBUS_FMT_Y10_1X10,
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- V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE,
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- V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_LE,
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- V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE,
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- V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE,
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- V4L2_MBUS_FMT_SGRBG8_1X8,
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- V4L2_MBUS_FMT_SBGGR12_1X12,
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- V4L2_MBUS_FMT_YUYV8_1_5X8,
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- V4L2_MBUS_FMT_YVYU8_1_5X8,
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- V4L2_MBUS_FMT_UYVY8_1_5X8,
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- V4L2_MBUS_FMT_VYUY8_1_5X8,
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+ V4L2_MBUS_FMT_FIXED = 0x0001,
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+
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+ /* RGB - next is 0x1009 */
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+ V4L2_MBUS_FMT_RGB444_2X8_PADHI_BE = 0x1001,
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+ V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE = 0x1002,
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+ V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE = 0x1003,
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+ V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE = 0x1004,
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+ V4L2_MBUS_FMT_BGR565_2X8_BE = 0x1005,
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+ V4L2_MBUS_FMT_BGR565_2X8_LE = 0x1006,
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+ V4L2_MBUS_FMT_RGB565_2X8_BE = 0x1007,
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+ V4L2_MBUS_FMT_RGB565_2X8_LE = 0x1008,
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+
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+ /* YUV (including grey) - next is 0x200f */
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+ V4L2_MBUS_FMT_Y8_1X8 = 0x2001,
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+ V4L2_MBUS_FMT_UYVY8_1_5X8 = 0x2002,
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+ V4L2_MBUS_FMT_VYUY8_1_5X8 = 0x2003,
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+ V4L2_MBUS_FMT_YUYV8_1_5X8 = 0x2004,
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+ V4L2_MBUS_FMT_YVYU8_1_5X8 = 0x2005,
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+ V4L2_MBUS_FMT_UYVY8_2X8 = 0x2006,
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+ V4L2_MBUS_FMT_VYUY8_2X8 = 0x2007,
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+ V4L2_MBUS_FMT_YUYV8_2X8 = 0x2008,
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+ V4L2_MBUS_FMT_YVYU8_2X8 = 0x2009,
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+ V4L2_MBUS_FMT_Y10_1X10 = 0x200a,
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+ V4L2_MBUS_FMT_YUYV10_2X10 = 0x200b,
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+ V4L2_MBUS_FMT_YVYU10_2X10 = 0x200c,
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+ V4L2_MBUS_FMT_YUYV10_1X20 = 0x200d,
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+ V4L2_MBUS_FMT_YVYU10_1X20 = 0x200e,
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+
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+ /* Bayer - next is 0x3009 */
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+ V4L2_MBUS_FMT_SBGGR8_1X8 = 0x3001,
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+ V4L2_MBUS_FMT_SGRBG8_1X8 = 0x3002,
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+ V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE = 0x3003,
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+ V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE = 0x3004,
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+ V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE = 0x3005,
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+ V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_LE = 0x3006,
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+ V4L2_MBUS_FMT_SBGGR10_1X10 = 0x3007,
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+ V4L2_MBUS_FMT_SBGGR12_1X12 = 0x3008,
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};
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/**
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