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@@ -313,6 +313,14 @@ static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
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[TSU_ADRL31] = 0x01fc,
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};
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+static int sh_eth_is_gether(struct sh_eth_private *mdp)
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+{
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+ if (mdp->reg_offset == sh_eth_offset_gigabit)
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+ return 1;
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+ else
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+ return 0;
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+}
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+
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static void __maybe_unused sh_eth_select_mii(struct net_device *ndev)
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{
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u32 value = 0x0;
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@@ -349,7 +357,6 @@ static void __maybe_unused sh_eth_set_duplex(struct net_device *ndev)
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/* There is CPU dependent code */
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#if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779)
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-#define SH_ETH_RESET_DEFAULT 1
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static void sh_eth_set_rate(struct net_device *ndev)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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@@ -386,7 +393,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
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.hw_swap = 1,
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};
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#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
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-#define SH_ETH_RESET_DEFAULT 1
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static void sh_eth_set_rate(struct net_device *ndev)
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{
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@@ -427,7 +433,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
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};
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#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
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#define SH_ETH_HAS_BOTH_MODULES 1
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-static int sh_eth_check_reset(struct net_device *ndev);
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static void sh_eth_set_rate(struct net_device *ndev)
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{
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@@ -493,42 +498,6 @@ static void sh_eth_chip_reset_giga(struct net_device *ndev)
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}
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}
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-static int sh_eth_is_gether(struct sh_eth_private *mdp);
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-static int sh_eth_reset(struct net_device *ndev)
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-{
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- struct sh_eth_private *mdp = netdev_priv(ndev);
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- int ret = 0;
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-
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- if (sh_eth_is_gether(mdp)) {
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- sh_eth_write(ndev, EDSR_ENALL, EDSR);
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- sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
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- EDMR);
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-
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- ret = sh_eth_check_reset(ndev);
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- if (ret)
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- goto out;
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-
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- /* Table Init */
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- sh_eth_write(ndev, 0x0, TDLAR);
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- sh_eth_write(ndev, 0x0, TDFAR);
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- sh_eth_write(ndev, 0x0, TDFXR);
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- sh_eth_write(ndev, 0x0, TDFFR);
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- sh_eth_write(ndev, 0x0, RDLAR);
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- sh_eth_write(ndev, 0x0, RDFAR);
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- sh_eth_write(ndev, 0x0, RDFXR);
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- sh_eth_write(ndev, 0x0, RDFFR);
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- } else {
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- sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
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- EDMR);
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- mdelay(3);
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- sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
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- EDMR);
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- }
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-
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-out:
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- return ret;
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-}
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-
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static void sh_eth_set_rate_giga(struct net_device *ndev)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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@@ -589,8 +558,6 @@ static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763)
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-static int sh_eth_check_reset(struct net_device *ndev);
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-static void sh_eth_reset_hw_crc(struct net_device *ndev);
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static void sh_eth_chip_reset(struct net_device *ndev)
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{
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@@ -653,45 +620,8 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
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#endif
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};
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-static int sh_eth_reset(struct net_device *ndev)
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-{
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- int ret = 0;
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-
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- sh_eth_write(ndev, EDSR_ENALL, EDSR);
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- sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
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-
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- ret = sh_eth_check_reset(ndev);
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- if (ret)
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- goto out;
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-
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- /* Table Init */
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- sh_eth_write(ndev, 0x0, TDLAR);
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- sh_eth_write(ndev, 0x0, TDFAR);
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- sh_eth_write(ndev, 0x0, TDFXR);
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- sh_eth_write(ndev, 0x0, TDFFR);
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- sh_eth_write(ndev, 0x0, RDLAR);
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- sh_eth_write(ndev, 0x0, RDFAR);
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- sh_eth_write(ndev, 0x0, RDFXR);
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- sh_eth_write(ndev, 0x0, RDFFR);
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-
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- /* Reset HW CRC register */
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- sh_eth_reset_hw_crc(ndev);
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-
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- /* Select MII mode */
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- if (sh_eth_my_cpu_data.select_mii)
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- sh_eth_select_mii(ndev);
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-out:
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- return ret;
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-}
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-
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-static void sh_eth_reset_hw_crc(struct net_device *ndev)
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-{
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- if (sh_eth_my_cpu_data.hw_crc)
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- sh_eth_write(ndev, 0x0, CSMR);
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-}
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#elif defined(CONFIG_ARCH_R8A7740)
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-static int sh_eth_check_reset(struct net_device *ndev);
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static void sh_eth_chip_reset(struct net_device *ndev)
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{
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@@ -704,31 +634,6 @@ static void sh_eth_chip_reset(struct net_device *ndev)
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sh_eth_select_mii(ndev);
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}
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-static int sh_eth_reset(struct net_device *ndev)
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-{
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- int ret = 0;
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-
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- sh_eth_write(ndev, EDSR_ENALL, EDSR);
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- sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
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-
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- ret = sh_eth_check_reset(ndev);
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- if (ret)
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- goto out;
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-
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- /* Table Init */
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- sh_eth_write(ndev, 0x0, TDLAR);
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- sh_eth_write(ndev, 0x0, TDFAR);
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- sh_eth_write(ndev, 0x0, TDFXR);
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- sh_eth_write(ndev, 0x0, TDFFR);
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- sh_eth_write(ndev, 0x0, RDLAR);
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- sh_eth_write(ndev, 0x0, RDFAR);
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- sh_eth_write(ndev, 0x0, RDFXR);
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- sh_eth_write(ndev, 0x0, RDFFR);
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-
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-out:
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- return ret;
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-}
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-
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static void sh_eth_set_rate(struct net_device *ndev)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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@@ -777,7 +682,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
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};
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#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
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-#define SH_ETH_RESET_DEFAULT 1
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static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
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.eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
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@@ -787,7 +691,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
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.hw_swap = 1,
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};
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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-#define SH_ETH_RESET_DEFAULT 1
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static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
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.eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
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.tsu = 1,
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@@ -822,17 +725,6 @@ static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
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cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
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}
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-#if defined(SH_ETH_RESET_DEFAULT)
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-/* Chip Reset */
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-static int sh_eth_reset(struct net_device *ndev)
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-{
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- sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
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- mdelay(3);
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- sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
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-
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- return 0;
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-}
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-#else
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static int sh_eth_check_reset(struct net_device *ndev)
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{
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int ret = 0;
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@@ -850,7 +742,49 @@ static int sh_eth_check_reset(struct net_device *ndev)
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}
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return ret;
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}
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-#endif
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+
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+static int sh_eth_reset(struct net_device *ndev)
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+{
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+ struct sh_eth_private *mdp = netdev_priv(ndev);
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+ int ret = 0;
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+
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+ if (sh_eth_is_gether(mdp)) {
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+ sh_eth_write(ndev, EDSR_ENALL, EDSR);
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+ sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
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+ EDMR);
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+
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+ ret = sh_eth_check_reset(ndev);
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+ if (ret)
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+ goto out;
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+
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+ /* Table Init */
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+ sh_eth_write(ndev, 0x0, TDLAR);
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+ sh_eth_write(ndev, 0x0, TDFAR);
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+ sh_eth_write(ndev, 0x0, TDFXR);
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+ sh_eth_write(ndev, 0x0, TDFFR);
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+ sh_eth_write(ndev, 0x0, RDLAR);
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+ sh_eth_write(ndev, 0x0, RDFAR);
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+ sh_eth_write(ndev, 0x0, RDFXR);
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+ sh_eth_write(ndev, 0x0, RDFFR);
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+
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+ /* Reset HW CRC register */
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+ if (mdp->cd->hw_crc)
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+ sh_eth_write(ndev, 0x0, CSMR);
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+
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+ /* Select MII mode */
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+ if (mdp->cd->select_mii)
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+ sh_eth_select_mii(ndev);
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+ } else {
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+ sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
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+ EDMR);
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+ mdelay(3);
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+ sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
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+ EDMR);
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+ }
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+
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+out:
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+ return ret;
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+}
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#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
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static void sh_eth_set_receive_align(struct sk_buff *skb)
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@@ -926,14 +860,6 @@ static void read_mac_address(struct net_device *ndev, unsigned char *mac)
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}
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}
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-static int sh_eth_is_gether(struct sh_eth_private *mdp)
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-{
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- if (mdp->reg_offset == sh_eth_offset_gigabit)
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- return 1;
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- else
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- return 0;
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-}
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-
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static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
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{
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if (sh_eth_is_gether(mdp))
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