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@@ -934,33 +934,29 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
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void cx231xx_enable656(struct cx231xx *dev)
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{
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u8 temp = 0;
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- int status;
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/*enable TS1 data[0:7] as output to export 656*/
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- status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
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+ vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
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/*enable TS1 clock as output to export 656*/
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- status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
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+ vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
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temp = temp|0x04;
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- status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
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-
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+ vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
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}
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EXPORT_SYMBOL_GPL(cx231xx_enable656);
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void cx231xx_disable656(struct cx231xx *dev)
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{
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u8 temp = 0;
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- int status;
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-
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- status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
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+ vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
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- status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
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+ vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
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temp = temp&0xFB;
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- status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
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+ vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
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}
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EXPORT_SYMBOL_GPL(cx231xx_disable656);
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@@ -1320,117 +1316,115 @@ void update_HH_register_after_set_DIF(struct cx231xx *dev)
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void cx231xx_dump_HH_reg(struct cx231xx *dev)
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{
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- u8 status = 0;
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u32 value = 0;
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u16 i = 0;
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value = 0x45005390;
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- status = vid_blk_write_word(dev, 0x104, value);
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+ vid_blk_write_word(dev, 0x104, value);
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for (i = 0x100; i < 0x140; i++) {
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- status = vid_blk_read_word(dev, i, &value);
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+ vid_blk_read_word(dev, i, &value);
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cx231xx_info("reg0x%x=0x%x\n", i, value);
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i = i+3;
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}
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for (i = 0x300; i < 0x400; i++) {
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- status = vid_blk_read_word(dev, i, &value);
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+ vid_blk_read_word(dev, i, &value);
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cx231xx_info("reg0x%x=0x%x\n", i, value);
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i = i+3;
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}
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for (i = 0x400; i < 0x440; i++) {
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- status = vid_blk_read_word(dev, i, &value);
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+ vid_blk_read_word(dev, i, &value);
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cx231xx_info("reg0x%x=0x%x\n", i, value);
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i = i+3;
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}
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- status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
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+ vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
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cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
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vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
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- status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
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+ vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
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cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
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}
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void cx231xx_dump_SC_reg(struct cx231xx *dev)
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{
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u8 value[4] = { 0, 0, 0, 0 };
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- int status = 0;
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cx231xx_info("cx231xx_dump_SC_reg!\n");
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
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value[1], value[2], value[3]);
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- status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
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+ cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
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value, 4);
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cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
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value[1], value[2], value[3]);
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@@ -1441,18 +1435,15 @@ void cx231xx_dump_SC_reg(struct cx231xx *dev)
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void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
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{
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- u8 status = 0;
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u8 value = 0;
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-
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-
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- status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
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+ afe_read_byte(dev, ADC_STATUS2_CH3, &value);
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value = (value & 0xFE)|0x01;
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- status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
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+ afe_write_byte(dev, ADC_STATUS2_CH3, value);
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- status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
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+ afe_read_byte(dev, ADC_STATUS2_CH3, &value);
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value = (value & 0xFE)|0x00;
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- status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
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+ afe_write_byte(dev, ADC_STATUS2_CH3, value);
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/*
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@@ -1464,44 +1455,43 @@ void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
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for low-if agc defect
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*/
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- status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
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+ afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
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value = (value & 0xFC)|0x00;
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- status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
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+ afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
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- status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
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+ afe_read_byte(dev, ADC_INPUT_CH3, &value);
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value = (value & 0xF9)|0x02;
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- status = afe_write_byte(dev, ADC_INPUT_CH3, value);
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+ afe_write_byte(dev, ADC_INPUT_CH3, value);
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- status = afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
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+ afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
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value = (value & 0xFB)|0x04;
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- status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
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+ afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
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- status = afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
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+ afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
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value = (value & 0xFC)|0x03;
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- status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
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+ afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
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- status = afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
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+ afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
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value = (value & 0xFB)|0x04;
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- status = afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
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+ afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
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- status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
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+ afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
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value = (value & 0xF8)|0x06;
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- status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
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+ afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
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- status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
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+ afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
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value = (value & 0x8F)|0x40;
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- status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
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+ afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
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- status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
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+ afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
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value = (value & 0xDF)|0x20;
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- status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
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+ afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
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}
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void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
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u8 spectral_invert, u32 mode)
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{
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u32 colibri_carrier_offset = 0;
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- u8 status = 0;
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u32 func_mode = 0x01; /* Device has a DIF if this function is called */
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u32 standard = 0;
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u8 value[4] = { 0, 0, 0, 0 };
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@@ -1511,15 +1501,15 @@ void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
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value[1] = (u8) 0x6F;
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value[2] = (u8) 0x6F;
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value[3] = (u8) 0x6F;
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- status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
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+ cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
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PWR_CTL_EN, value, 4);
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/*Set colibri for low IF*/
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- status = cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
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+ cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
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/* Set C2HH for low IF operation.*/
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standard = dev->norm;
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- status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
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+ cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
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func_mode, standard);
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/* Get colibri offsets.*/
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@@ -1556,7 +1546,6 @@ void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
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u8 spectral_invert, u32 mode)
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{
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unsigned long pll_freq_word;
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- int status = 0;
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u32 dif_misc_ctrl_value = 0;
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u64 pll_freq_u64 = 0;
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u32 i = 0;
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@@ -1567,7 +1556,7 @@ void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
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if (mode == TUNER_MODE_FM_RADIO) {
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pll_freq_word = 0x905A1CAC;
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- status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
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+ vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
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} else /*KSPROPERTY_TUNER_MODE_TV*/{
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/* Calculate the PLL frequency word based on the adjusted if_freq*/
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@@ -1576,23 +1565,23 @@ void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
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do_div(pll_freq_u64, 50000000);
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pll_freq_word = (u32)pll_freq_u64;
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/*pll_freq_word = 0x3463497;*/
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- status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
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+ vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
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if (spectral_invert) {
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if_freq -= 400000;
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/* Enable Spectral Invert*/
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- status = vid_blk_read_word(dev, DIF_MISC_CTRL,
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+ vid_blk_read_word(dev, DIF_MISC_CTRL,
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&dif_misc_ctrl_value);
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dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
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- status = vid_blk_write_word(dev, DIF_MISC_CTRL,
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+ vid_blk_write_word(dev, DIF_MISC_CTRL,
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dif_misc_ctrl_value);
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} else {
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if_freq += 400000;
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/* Disable Spectral Invert*/
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- status = vid_blk_read_word(dev, DIF_MISC_CTRL,
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+ vid_blk_read_word(dev, DIF_MISC_CTRL,
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&dif_misc_ctrl_value);
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dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
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- status = vid_blk_write_word(dev, DIF_MISC_CTRL,
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+ vid_blk_write_word(dev, DIF_MISC_CTRL,
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dif_misc_ctrl_value);
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}
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@@ -1609,7 +1598,7 @@ void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
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sizeof(Dif_set_array)/sizeof(struct dif_settings));
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for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) {
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if (Dif_set_array[i].if_freq == if_freq) {
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- status = vid_blk_write_word(dev,
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+ vid_blk_write_word(dev,
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Dif_set_array[i].register_address, Dif_set_array[i].value);
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}
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}
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@@ -3090,31 +3079,30 @@ int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
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*/
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int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
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{
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- int status = 0;
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int i = 0;
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/* get the lock */
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mutex_lock(&dev->gpio_i2c_lock);
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/* start */
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- status = cx231xx_gpio_i2c_start(dev);
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+ cx231xx_gpio_i2c_start(dev);
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/* write dev_addr */
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- status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
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+ cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
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/* read Ack */
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- status = cx231xx_gpio_i2c_read_ack(dev);
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+ cx231xx_gpio_i2c_read_ack(dev);
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for (i = 0; i < len; i++) {
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/* Write data */
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- status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
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+ cx231xx_gpio_i2c_write_byte(dev, buf[i]);
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/* read Ack */
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- status = cx231xx_gpio_i2c_read_ack(dev);
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+ cx231xx_gpio_i2c_read_ack(dev);
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}
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/* write End */
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- status = cx231xx_gpio_i2c_end(dev);
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+ cx231xx_gpio_i2c_end(dev);
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/* release the lock */
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mutex_unlock(&dev->gpio_i2c_lock);
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