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@@ -1448,10 +1448,6 @@ static u32
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si_pmu1_cpuclk0(si_t *sih, chipcregs_t *cc)
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{
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u32 tmp, m1div;
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-#ifdef BCMDBG
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- u32 ndiv_int, ndiv_frac, p2div, p1div, fvco;
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- u32 fref;
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-#endif
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u32 FVCO = si_pmu1_pllfvco0(sih);
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/* Read m1div from pllcontrol[1] */
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@@ -1459,41 +1455,6 @@ si_pmu1_cpuclk0(si_t *sih, chipcregs_t *cc)
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tmp = R_REG(&cc->pllcontrol_data);
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m1div = (tmp & PMU1_PLL0_PC1_M1DIV_MASK) >> PMU1_PLL0_PC1_M1DIV_SHIFT;
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-#ifdef BCMDBG
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- /* Read p2div/p1div from pllcontrol[0] */
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- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
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- tmp = R_REG(&cc->pllcontrol_data);
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- p2div = (tmp & PMU1_PLL0_PC0_P2DIV_MASK) >> PMU1_PLL0_PC0_P2DIV_SHIFT;
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- p1div = (tmp & PMU1_PLL0_PC0_P1DIV_MASK) >> PMU1_PLL0_PC0_P1DIV_SHIFT;
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-
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- /* Calculate fvco based on xtal freq and ndiv and pdiv */
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- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
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- tmp = R_REG(&cc->pllcontrol_data);
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- ndiv_int =
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- (tmp & PMU1_PLL0_PC2_NDIV_INT_MASK) >> PMU1_PLL0_PC2_NDIV_INT_SHIFT;
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-
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- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
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- tmp = R_REG(&cc->pllcontrol_data);
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- ndiv_frac =
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- (tmp & PMU1_PLL0_PC3_NDIV_FRAC_MASK) >>
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- PMU1_PLL0_PC3_NDIV_FRAC_SHIFT;
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-
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- fref = si_pmu1_alpclk0(sih, cc) / 1000;
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-
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- fvco = (fref * ndiv_int) << 8;
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- fvco += (fref * (ndiv_frac >> 12)) >> 4;
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- fvco += (fref * (ndiv_frac & 0xfff)) >> 12;
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- fvco >>= 8;
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- fvco *= p2div;
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- fvco /= p1div;
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- fvco /= 1000;
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- fvco *= 1000;
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-
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- PMU_MSG(("si_pmu1_cpuclk0: ndiv_int %u ndiv_frac %u p2div %u p1div %u fvco %u\n", ndiv_int, ndiv_frac, p2div, p1div, fvco));
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-
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- FVCO = fvco;
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-#endif /* BCMDBG */
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-
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/* Return ARM/SB clock */
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return FVCO / m1div * 1000;
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}
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