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@@ -80,7 +80,6 @@
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#define __LC_USER_ASCE 0xC50
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#define __LC_USER_ASCE 0xC50
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#define __LC_PANIC_STACK 0xC54
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#define __LC_PANIC_STACK 0xC54
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#define __LC_CPUID 0xC60
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#define __LC_CPUID 0xC60
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-#define __LC_IPLDEV 0xC7C
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#define __LC_CURRENT 0xC90
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#define __LC_CURRENT 0xC90
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#define __LC_INT_CLOCK 0xC98
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#define __LC_INT_CLOCK 0xC98
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#else /* __s390x__ */
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#else /* __s390x__ */
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@@ -101,7 +100,6 @@
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#define __LC_USER_ASCE 0xD60
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#define __LC_USER_ASCE 0xD60
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#define __LC_PANIC_STACK 0xD68
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#define __LC_PANIC_STACK 0xD68
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#define __LC_CPUID 0xD80
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#define __LC_CPUID 0xD80
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-#define __LC_IPLDEV 0xDB8
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#define __LC_CURRENT 0xDD8
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#define __LC_CURRENT 0xDD8
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#define __LC_INT_CLOCK 0xDE8
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#define __LC_INT_CLOCK 0xDE8
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#define __LC_VDSO_PER_CPU 0xE38
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#define __LC_VDSO_PER_CPU 0xE38
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@@ -273,8 +271,7 @@ struct _lowcore
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/* entry.S sensitive area start */
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/* entry.S sensitive area start */
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cpuid_t cpu_id; /* 0xc60 */
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cpuid_t cpu_id; /* 0xc60 */
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__u32 cpu_nr; /* 0xc68 */
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__u32 cpu_nr; /* 0xc68 */
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- __u32 ipl_device; /* 0xc6c */
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- __u8 pad_0xc70[0xc80-0xc70]; /* 0xc70 */
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+ __u8 pad_0xc6c[0xc80-0xc6c]; /* 0xc6c */
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/* entry.S sensitive area end */
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/* entry.S sensitive area end */
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/* SMP info area: defined by DJB */
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/* SMP info area: defined by DJB */
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@@ -368,8 +365,7 @@ struct _lowcore
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/* entry.S sensitive area start */
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/* entry.S sensitive area start */
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cpuid_t cpu_id; /* 0xd80 */
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cpuid_t cpu_id; /* 0xd80 */
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__u32 cpu_nr; /* 0xd88 */
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__u32 cpu_nr; /* 0xd88 */
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- __u32 ipl_device; /* 0xd8c */
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- __u8 pad_0xd90[0xdc0-0xd90]; /* 0xd90 */
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+ __u8 pad_0xd8c[0xdc0-0xd8c]; /* 0xd8c */
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/* entry.S sensitive area end */
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/* entry.S sensitive area end */
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/* SMP info area: defined by DJB */
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/* SMP info area: defined by DJB */
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