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@@ -220,7 +220,7 @@ static int pcie_init(struct sh7786_pcie_port *port)
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unsigned int data;
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phys_addr_t memphys;
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size_t memsize;
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- int ret, i;
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+ int ret, i, win;
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/* Begin initialization */
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pcie_reset(port);
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@@ -337,13 +337,19 @@ static int pcie_init(struct sh7786_pcie_port *port)
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printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
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port->index, (data >> 20) & 0x3f);
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-
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- for (i = 0; i < chan->nr_resources; i++) {
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+ for (i = win = 0; i < chan->nr_resources; i++) {
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struct resource *res = chan->resources + i;
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resource_size_t size;
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u32 enable_mask;
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- pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(i));
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+ /*
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+ * We can't use the 32-bit mode windows in legacy 29-bit
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+ * mode, so just skip them entirely.
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+ */
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+ if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode())
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+ continue;
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+
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+ pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
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size = resource_size(res);
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@@ -352,16 +358,18 @@ static int pcie_init(struct sh7786_pcie_port *port)
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* keeps things pretty simple.
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*/
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__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
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- chan->reg_base + SH4A_PCIEPAMR(i));
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+ chan->reg_base + SH4A_PCIEPAMR(win));
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- pci_write_reg(chan, res->start, SH4A_PCIEPARL(i));
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- pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(i));
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+ pci_write_reg(chan, res->start, SH4A_PCIEPARL(win));
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+ pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(win));
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enable_mask = MASK_PARE;
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if (res->flags & IORESOURCE_IO)
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enable_mask |= MASK_SPC;
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- pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(i));
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+ pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(win));
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+
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+ win++;
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}
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return 0;
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