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@@ -708,7 +708,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
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struct radeon_connector_atom_dig *dig_connector =
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radeon_get_atom_connector_priv_from_encoder(encoder);
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union dig_encoder_control args;
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- int index = 0, num = 0;
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+ int index = 0;
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uint8_t frev, crev;
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if (!dig || !dig_connector)
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@@ -724,7 +724,6 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
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else
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index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
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}
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- num = dig->dig_encoder + 1;
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if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
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return;
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@@ -786,7 +785,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
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struct drm_connector *connector;
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struct radeon_connector *radeon_connector;
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union dig_transmitter_control args;
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- int index = 0, num = 0;
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+ int index = 0;
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uint8_t frev, crev;
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bool is_dp = false;
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int pll_id = 0;
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@@ -862,15 +861,12 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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args.v3.acConfig.ucTransmitterSel = 0;
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- num = 0;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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args.v3.acConfig.ucTransmitterSel = 1;
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- num = 1;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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args.v3.acConfig.ucTransmitterSel = 2;
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- num = 2;
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break;
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}
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@@ -881,23 +877,19 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
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args.v3.acConfig.fCoherentMode = 1;
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}
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} else if (ASIC_IS_DCE32(rdev)) {
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- if (dig->dig_encoder == 1)
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- args.v2.acConfig.ucEncoderSel = 1;
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+ args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
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if (dig_connector->linkb)
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args.v2.acConfig.ucLinkSel = 1;
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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args.v2.acConfig.ucTransmitterSel = 0;
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- num = 0;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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args.v2.acConfig.ucTransmitterSel = 1;
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- num = 1;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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args.v2.acConfig.ucTransmitterSel = 2;
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- num = 2;
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break;
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}
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@@ -915,31 +907,25 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
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else
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
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- switch (radeon_encoder->encoder_id) {
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- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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- if (rdev->flags & RADEON_IS_IGP) {
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- if (radeon_encoder->pixel_clock > 165000) {
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- if (dig_connector->igp_lane_info & 0x3)
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- args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
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- else if (dig_connector->igp_lane_info & 0xc)
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- args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
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- } else {
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- if (dig_connector->igp_lane_info & 0x1)
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- args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
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- else if (dig_connector->igp_lane_info & 0x2)
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- args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
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- else if (dig_connector->igp_lane_info & 0x4)
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- args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
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- else if (dig_connector->igp_lane_info & 0x8)
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- args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
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- }
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+ if ((rdev->flags & RADEON_IS_IGP) &&
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+ (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
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+ if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
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+ if (dig_connector->igp_lane_info & 0x1)
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+ args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
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+ else if (dig_connector->igp_lane_info & 0x2)
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+ args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
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+ else if (dig_connector->igp_lane_info & 0x4)
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+ args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
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+ else if (dig_connector->igp_lane_info & 0x8)
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+ args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
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+ } else {
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+ if (dig_connector->igp_lane_info & 0x3)
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+ args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
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+ else if (dig_connector->igp_lane_info & 0xc)
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+ args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
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}
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- break;
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}
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- if (radeon_encoder->pixel_clock > 165000)
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- args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
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-
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if (dig_connector->linkb)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
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else
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@@ -950,6 +936,8 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
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else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
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if (dig->coherent_mode)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
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+ if (radeon_encoder->pixel_clock > 165000)
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+ args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
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}
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}
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