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@@ -1553,7 +1553,8 @@
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#define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */
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#define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */
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#define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */
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-#define IXGBE_MTQC_64VF 0x8 /* 2 TX Queues per pool w/64VF's */
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+#define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */
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+#define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */
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#define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
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/* Receive Descriptor bit definitions */
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