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@@ -1,7 +1,6 @@
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-/* $Id: spitfire.h,v 1.18 2001/11/29 16:42:10 kanoj Exp $
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- * spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
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+/* spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
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*
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- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
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+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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*/
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#ifndef _SPARC64_SPITFIRE_H
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@@ -67,7 +66,7 @@ extern void cheetah_enable_pcache(void);
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/* The data cache is write through, so this just invalidates the
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* specified line.
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*/
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-static __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
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+static inline void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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@@ -81,7 +80,7 @@ static __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long
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* a flush instruction (to any address) is sufficient to handle
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* this issue after the line is invalidated.
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*/
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-static __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
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+static inline void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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@@ -89,7 +88,7 @@ static __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long
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: "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
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}
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-static __inline__ unsigned long spitfire_get_dtlb_data(int entry)
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+static inline unsigned long spitfire_get_dtlb_data(int entry)
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{
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unsigned long data;
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@@ -103,7 +102,7 @@ static __inline__ unsigned long spitfire_get_dtlb_data(int entry)
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return data;
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}
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-static __inline__ unsigned long spitfire_get_dtlb_tag(int entry)
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+static inline unsigned long spitfire_get_dtlb_tag(int entry)
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{
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unsigned long tag;
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@@ -113,7 +112,7 @@ static __inline__ unsigned long spitfire_get_dtlb_tag(int entry)
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return tag;
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}
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-static __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data)
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+static inline void spitfire_put_dtlb_data(int entry, unsigned long data)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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@@ -122,7 +121,7 @@ static __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data)
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"i" (ASI_DTLB_DATA_ACCESS));
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}
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-static __inline__ unsigned long spitfire_get_itlb_data(int entry)
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+static inline unsigned long spitfire_get_itlb_data(int entry)
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{
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unsigned long data;
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@@ -136,7 +135,7 @@ static __inline__ unsigned long spitfire_get_itlb_data(int entry)
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return data;
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}
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-static __inline__ unsigned long spitfire_get_itlb_tag(int entry)
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+static inline unsigned long spitfire_get_itlb_tag(int entry)
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{
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unsigned long tag;
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@@ -146,7 +145,7 @@ static __inline__ unsigned long spitfire_get_itlb_tag(int entry)
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return tag;
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}
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-static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data)
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+static inline void spitfire_put_itlb_data(int entry, unsigned long data)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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@@ -155,7 +154,7 @@ static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data)
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"i" (ASI_ITLB_DATA_ACCESS));
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}
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-static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page)
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+static inline void spitfire_flush_dtlb_nucleus_page(unsigned long page)
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{
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__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
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"membar #Sync"
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@@ -163,7 +162,7 @@ static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page)
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: "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
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}
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-static __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page)
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+static inline void spitfire_flush_itlb_nucleus_page(unsigned long page)
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{
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__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
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"membar #Sync"
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@@ -172,7 +171,7 @@ static __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page)
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}
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/* Cheetah has "all non-locked" tlb flushes. */
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-static __inline__ void cheetah_flush_dtlb_all(void)
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+static inline void cheetah_flush_dtlb_all(void)
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{
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__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
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"membar #Sync"
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@@ -180,7 +179,7 @@ static __inline__ void cheetah_flush_dtlb_all(void)
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: "r" (0x80), "i" (ASI_DMMU_DEMAP));
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}
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-static __inline__ void cheetah_flush_itlb_all(void)
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+static inline void cheetah_flush_itlb_all(void)
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{
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__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
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"membar #Sync"
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@@ -202,7 +201,7 @@ static __inline__ void cheetah_flush_itlb_all(void)
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* ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
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* the problem for me. -DaveM
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*/
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-static __inline__ unsigned long cheetah_get_ldtlb_data(int entry)
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+static inline unsigned long cheetah_get_ldtlb_data(int entry)
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{
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unsigned long data;
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@@ -215,7 +214,7 @@ static __inline__ unsigned long cheetah_get_ldtlb_data(int entry)
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return data;
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}
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-static __inline__ unsigned long cheetah_get_litlb_data(int entry)
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+static inline unsigned long cheetah_get_litlb_data(int entry)
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{
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unsigned long data;
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@@ -228,7 +227,7 @@ static __inline__ unsigned long cheetah_get_litlb_data(int entry)
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return data;
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}
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-static __inline__ unsigned long cheetah_get_ldtlb_tag(int entry)
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+static inline unsigned long cheetah_get_ldtlb_tag(int entry)
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{
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unsigned long tag;
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@@ -240,7 +239,7 @@ static __inline__ unsigned long cheetah_get_ldtlb_tag(int entry)
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return tag;
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}
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-static __inline__ unsigned long cheetah_get_litlb_tag(int entry)
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+static inline unsigned long cheetah_get_litlb_tag(int entry)
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{
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unsigned long tag;
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@@ -252,7 +251,7 @@ static __inline__ unsigned long cheetah_get_litlb_tag(int entry)
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return tag;
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}
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-static __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data)
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+static inline void cheetah_put_ldtlb_data(int entry, unsigned long data)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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@@ -262,7 +261,7 @@ static __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data)
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"i" (ASI_DTLB_DATA_ACCESS));
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}
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-static __inline__ void cheetah_put_litlb_data(int entry, unsigned long data)
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+static inline void cheetah_put_litlb_data(int entry, unsigned long data)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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@@ -272,7 +271,7 @@ static __inline__ void cheetah_put_litlb_data(int entry, unsigned long data)
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"i" (ASI_ITLB_DATA_ACCESS));
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}
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-static __inline__ unsigned long cheetah_get_dtlb_data(int entry, int tlb)
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+static inline unsigned long cheetah_get_dtlb_data(int entry, int tlb)
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{
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unsigned long data;
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@@ -284,7 +283,7 @@ static __inline__ unsigned long cheetah_get_dtlb_data(int entry, int tlb)
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return data;
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}
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-static __inline__ unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
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+static inline unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
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{
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unsigned long tag;
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@@ -294,7 +293,7 @@ static __inline__ unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
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return tag;
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}
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-static __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
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+static inline void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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@@ -304,7 +303,7 @@ static __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data, int
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"i" (ASI_DTLB_DATA_ACCESS));
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}
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-static __inline__ unsigned long cheetah_get_itlb_data(int entry)
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+static inline unsigned long cheetah_get_itlb_data(int entry)
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{
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unsigned long data;
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@@ -317,7 +316,7 @@ static __inline__ unsigned long cheetah_get_itlb_data(int entry)
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return data;
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}
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-static __inline__ unsigned long cheetah_get_itlb_tag(int entry)
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+static inline unsigned long cheetah_get_itlb_tag(int entry)
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{
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unsigned long tag;
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@@ -327,7 +326,7 @@ static __inline__ unsigned long cheetah_get_itlb_tag(int entry)
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return tag;
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}
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-static __inline__ void cheetah_put_itlb_data(int entry, unsigned long data)
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+static inline void cheetah_put_itlb_data(int entry, unsigned long data)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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