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@@ -25,7 +25,7 @@ set_render_target(struct radeon_device *rdev, int format,
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u32 cb_color_info;
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int pitch, slice;
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- h = (h + 7) & ~7;
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+ h = ALIGN(h, 8);
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if (h < 8)
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h = 8;
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@@ -396,7 +396,7 @@ set_default_state(struct radeon_device *rdev)
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NUM_ES_STACK_ENTRIES(num_es_stack_entries));
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/* emit an IB pointing at default state */
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- dwords = (rdev->r600_blit.state_len + 0xf) & ~0xf;
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+ dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
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gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
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radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
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radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
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