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@@ -1130,34 +1130,15 @@ exit:
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}
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#endif
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-static void smp_tune_scheduling (void)
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+static void smp_tune_scheduling(void)
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{
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unsigned long cachesize; /* kB */
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- unsigned long bandwidth = 350; /* MB/s */
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- /*
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- * Rough estimation for SMP scheduling, this is the number of
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- * cycles it takes for a fully memory-limited process to flush
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- * the SMP-local cache.
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- *
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- * (For a P5 this pretty much means we will choose another idle
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- * CPU almost always at wakeup time (this is due to the small
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- * L1 cache), on PIIs it's around 50-100 usecs, depending on
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- * the cache size)
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- */
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- if (!cpu_khz) {
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- /*
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- * this basically disables processor-affinity
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- * scheduling on SMP without a TSC.
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- */
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- return;
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- } else {
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+ if (cpu_khz) {
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cachesize = boot_cpu_data.x86_cache_size;
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- if (cachesize == -1) {
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- cachesize = 16; /* Pentiums, 2x8kB cache */
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- bandwidth = 100;
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- }
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- max_cache_size = cachesize * 1024;
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+
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+ if (cachesize > 0)
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+ max_cache_size = cachesize * 1024;
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}
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}
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