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@@ -233,7 +233,17 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
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bo->pin_count++;
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if (gpu_addr)
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*gpu_addr = radeon_bo_gpu_offset(bo);
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- WARN_ON_ONCE(max_offset != 0);
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+
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+ if (max_offset != 0) {
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+ u64 domain_start;
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+
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+ if (domain == RADEON_GEM_DOMAIN_VRAM)
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+ domain_start = bo->rdev->mc.vram_start;
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+ else
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+ domain_start = bo->rdev->mc.gtt_start;
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+ WARN_ON_ONCE((*gpu_addr - domain_start) > max_offset);
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+ }
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+
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return 0;
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}
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radeon_ttm_placement_from_domain(bo, domain);
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