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@@ -43,7 +43,7 @@
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/* Per channel configuration registers */
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-#define PL008_Cx_STRIDE (0x20)
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+#define PL080_Cx_STRIDE (0x20)
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#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
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#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20)))
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#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20)))
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@@ -68,6 +68,8 @@
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#define PL080_CONTROL_TC_IRQ_EN (1 << 31)
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#define PL080_CONTROL_PROT_MASK (0x7 << 28)
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#define PL080_CONTROL_PROT_SHIFT (28)
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+#define PL080_CONTROL_PROT_CACHE (1 << 30)
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+#define PL080_CONTROL_PROT_BUFF (1 << 29)
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#define PL080_CONTROL_PROT_SYS (1 << 28)
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#define PL080_CONTROL_DST_INCR (1 << 27)
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#define PL080_CONTROL_SRC_INCR (1 << 26)
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