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@@ -27,20 +27,23 @@
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*/
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#include <linux/kernel.h>
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-#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/types.h>
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-#include <linux/pci.h>
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#include <linux/spinlock.h>
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-#include <linux/io.h>
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#include <linux/platform_device.h>
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-
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-#include <asm/addrspace.h>
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+#include <linux/gpio.h>
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#include <asm/mach-rc32434/rb.h>
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-
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-struct rb532_gpio_reg __iomem *rb532_gpio_reg0;
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-EXPORT_SYMBOL(rb532_gpio_reg0);
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+#include <asm/mach-rc32434/gpio.h>
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+
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+struct rb532_gpio_chip {
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+ struct gpio_chip chip;
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+ void __iomem *regbase;
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+ void (*set_int_level)(struct gpio_chip *chip, unsigned offset, int value);
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+ int (*get_int_level)(struct gpio_chip *chip, unsigned offset);
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+ void (*set_int_status)(struct gpio_chip *chip, unsigned offset, int value);
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+ int (*get_int_status)(struct gpio_chip *chip, unsigned offset);
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+};
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struct mpmc_device dev3;
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@@ -108,108 +111,199 @@ unsigned char get_latch_u5(void)
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}
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EXPORT_SYMBOL(get_latch_u5);
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-int rb532_gpio_get_value(unsigned gpio)
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+/*
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+ * Return GPIO level */
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+static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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- return readl(&rb532_gpio_reg0->gpiod) & (1 << gpio);
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+ u32 mask = 1 << offset;
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+ struct rb532_gpio_chip *gpch;
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+
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+ gpch = container_of(chip, struct rb532_gpio_chip, chip);
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+ return readl(gpch->regbase + GPIOD) & mask;
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}
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-EXPORT_SYMBOL(rb532_gpio_get_value);
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-void rb532_gpio_set_value(unsigned gpio, int value)
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+/*
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+ * Set output GPIO level
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+ */
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+static void rb532_gpio_set(struct gpio_chip *chip,
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+ unsigned offset, int value)
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{
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- unsigned tmp;
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+ unsigned long flags;
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+ u32 mask = 1 << offset;
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+ u32 tmp;
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+ struct rb532_gpio_chip *gpch;
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+ void __iomem *gpvr;
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- tmp = readl(&rb532_gpio_reg0->gpiod) & ~(1 << gpio);
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- if (value)
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- tmp |= 1 << gpio;
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+ gpch = container_of(chip, struct rb532_gpio_chip, chip);
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+ gpvr = gpch->regbase + GPIOD;
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- writel(tmp, (void *)&rb532_gpio_reg0->gpiod);
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+ local_irq_save(flags);
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+ tmp = readl(gpvr);
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+ if (value)
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+ tmp |= mask;
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+ else
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+ tmp &= ~mask;
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+ writel(tmp, gpvr);
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+ local_irq_restore(flags);
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}
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-EXPORT_SYMBOL(rb532_gpio_set_value);
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-int rb532_gpio_direction_input(unsigned gpio)
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+/*
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+ * Set GPIO direction to input
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+ */
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+static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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- writel(readl(&rb532_gpio_reg0->gpiocfg) & ~(1 << gpio),
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- (void *)&rb532_gpio_reg0->gpiocfg);
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+ unsigned long flags;
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+ u32 mask = 1 << offset;
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+ u32 value;
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+ struct rb532_gpio_chip *gpch;
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+ void __iomem *gpdr;
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- return 0;
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-}
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-EXPORT_SYMBOL(rb532_gpio_direction_input);
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+ gpch = container_of(chip, struct rb532_gpio_chip, chip);
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+ gpdr = gpch->regbase + GPIOCFG;
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-int rb532_gpio_direction_output(unsigned gpio, int value)
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-{
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- gpio_set_value(gpio, value);
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- writel(readl(&rb532_gpio_reg0->gpiocfg) | (1 << gpio),
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- (void *)&rb532_gpio_reg0->gpiocfg);
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+ local_irq_save(flags);
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+ value = readl(gpdr);
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+ value &= ~mask;
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+ writel(value, gpdr);
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+ local_irq_restore(flags);
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return 0;
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}
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-EXPORT_SYMBOL(rb532_gpio_direction_output);
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-void rb532_gpio_set_int_level(unsigned gpio, int value)
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+/*
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+ * Set GPIO direction to output
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+ */
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+static int rb532_gpio_direction_output(struct gpio_chip *chip,
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+ unsigned offset, int value)
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{
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- unsigned tmp;
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+ unsigned long flags;
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+ u32 mask = 1 << offset;
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+ u32 tmp;
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+ struct rb532_gpio_chip *gpch;
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+ void __iomem *gpdr;
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+
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+ gpch = container_of(chip, struct rb532_gpio_chip, chip);
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+ writel(mask, gpch->regbase + GPIOD);
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+ gpdr = gpch->regbase + GPIOCFG;
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+
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+ local_irq_save(flags);
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+ tmp = readl(gpdr);
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+ tmp |= mask;
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+ writel(tmp, gpdr);
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+ local_irq_restore(flags);
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- tmp = readl(&rb532_gpio_reg0->gpioilevel) & ~(1 << gpio);
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- if (value)
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- tmp |= 1 << gpio;
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- writel(tmp, (void *)&rb532_gpio_reg0->gpioilevel);
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+ return 0;
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}
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-EXPORT_SYMBOL(rb532_gpio_set_int_level);
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-int rb532_gpio_get_int_level(unsigned gpio)
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+/*
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+ * Set the GPIO interrupt level
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+ */
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+static void rb532_gpio_set_int_level(struct gpio_chip *chip,
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+ unsigned offset, int value)
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{
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- return readl(&rb532_gpio_reg0->gpioilevel) & (1 << gpio);
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-}
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-EXPORT_SYMBOL(rb532_gpio_get_int_level);
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+ unsigned long flags;
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+ u32 mask = 1 << offset;
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+ u32 tmp;
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+ struct rb532_gpio_chip *gpch;
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+ void __iomem *gpil;
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-void rb532_gpio_set_int_status(unsigned gpio, int value)
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-{
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- unsigned tmp;
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+ gpch = container_of(chip, struct rb532_gpio_chip, chip);
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+ gpil = gpch->regbase + GPIOILEVEL;
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- tmp = readl(&rb532_gpio_reg0->gpioistat);
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+ local_irq_save(flags);
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+ tmp = readl(gpil);
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if (value)
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- tmp |= 1 << gpio;
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- writel(tmp, (void *)&rb532_gpio_reg0->gpioistat);
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+ tmp |= mask;
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+ else
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+ tmp &= ~mask;
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+ writel(tmp, gpil);
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+ local_irq_restore(flags);
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}
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-EXPORT_SYMBOL(rb532_gpio_set_int_status);
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-int rb532_gpio_get_int_status(unsigned gpio)
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+/*
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+ * Get the GPIO interrupt level
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+ */
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+static int rb532_gpio_get_int_level(struct gpio_chip *chip, unsigned offset)
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{
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- return readl(&rb532_gpio_reg0->gpioistat) & (1 << gpio);
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+ u32 mask = 1 << offset;
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+ struct rb532_gpio_chip *gpch;
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+
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+ gpch = container_of(chip, struct rb532_gpio_chip, chip);
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+ return readl(gpch->regbase + GPIOILEVEL) & mask;
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}
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-EXPORT_SYMBOL(rb532_gpio_get_int_status);
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-void rb532_gpio_set_func(unsigned gpio, int value)
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+/*
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+ * Set the GPIO interrupt status
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+ */
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+static void rb532_gpio_set_int_status(struct gpio_chip *chip,
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+ unsigned offset, int value)
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{
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- unsigned tmp;
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+ unsigned long flags;
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+ u32 mask = 1 << offset;
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+ u32 tmp;
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+ struct rb532_gpio_chip *gpch;
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+ void __iomem *gpis;
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+
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+ gpch = container_of(chip, struct rb532_gpio_chip, chip);
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+ gpis = gpch->regbase + GPIOISTAT;
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- tmp = readl(&rb532_gpio_reg0->gpiofunc);
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+ local_irq_save(flags);
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+ tmp = readl(gpis);
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if (value)
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- tmp |= 1 << gpio;
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- writel(tmp, (void *)&rb532_gpio_reg0->gpiofunc);
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+ tmp |= mask;
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+ else
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+ tmp &= ~mask;
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+ writel(tmp, gpis);
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+ local_irq_restore(flags);
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}
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-EXPORT_SYMBOL(rb532_gpio_set_func);
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-int rb532_gpio_get_func(unsigned gpio)
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+/*
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+ * Get the GPIO interrupt status
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+ */
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+static int rb532_gpio_get_int_status(struct gpio_chip *chip, unsigned offset)
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{
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- return readl(&rb532_gpio_reg0->gpiofunc) & (1 << gpio);
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+ u32 mask = 1 << offset;
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+ struct rb532_gpio_chip *gpch;
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+
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+ gpch = container_of(chip, struct rb532_gpio_chip, chip);
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+ return readl(gpch->regbase + GPIOISTAT) & mask;
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}
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-EXPORT_SYMBOL(rb532_gpio_get_func);
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+
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+static struct rb532_gpio_chip rb532_gpio_chip[] = {
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+ [0] = {
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+ .chip = {
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+ .label = "gpio0",
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+ .direction_input = rb532_gpio_direction_input,
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+ .direction_output = rb532_gpio_direction_output,
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+ .get = rb532_gpio_get,
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+ .set = rb532_gpio_set,
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+ .base = 0,
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+ .ngpio = 32,
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+ },
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+ .get_int_level = rb532_gpio_get_int_level,
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+ .set_int_level = rb532_gpio_set_int_level,
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+ .get_int_status = rb532_gpio_get_int_status,
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+ .set_int_status = rb532_gpio_set_int_status,
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+ },
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+};
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int __init rb532_gpio_init(void)
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{
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- rb532_gpio_reg0 = ioremap_nocache(rb532_gpio_reg0_res[0].start,
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- rb532_gpio_reg0_res[0].end -
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- rb532_gpio_reg0_res[0].start);
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+ struct resource *r;
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- if (!rb532_gpio_reg0) {
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+ r = rb532_gpio_reg0_res;
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+ rb532_gpio_chip->regbase = ioremap_nocache(r->start, r->end - r->start);
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+
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+ if (!rb532_gpio_chip->regbase) {
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printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
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return -ENXIO;
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}
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- dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start,
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- rb532_dev3_ctl_res[0].end -
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- rb532_dev3_ctl_res[0].start);
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+ /* Register our GPIO chip */
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+ gpiochip_add(&rb532_gpio_chip->chip);
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+
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+ r = rb532_dev3_ctl_res;
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+ dev3.base = ioremap_nocache(r->start, r->end - r->start);
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if (!dev3.base) {
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printk(KERN_ERR "rb532: cannot remap device controller 3\n");
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