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@@ -35,22 +35,27 @@ nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan)
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_bo *pb = chan->pushbuf_bo;
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struct nouveau_gpuobj *pushbuf = NULL;
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- uint32_t start = pb->bo.mem.mm_node->start << PAGE_SHIFT;
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int ret;
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+ if (dev_priv->card_type >= NV_50) {
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+ ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
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+ dev_priv->vm_end, NV_DMA_ACCESS_RO,
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+ NV_DMA_TARGET_AGP, &pushbuf);
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+ chan->pushbuf_base = pb->bo.offset;
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+ } else
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if (pb->bo.mem.mem_type == TTM_PL_TT) {
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ret = nouveau_gpuobj_gart_dma_new(chan, 0,
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dev_priv->gart_info.aper_size,
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NV_DMA_ACCESS_RO, &pushbuf,
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NULL);
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- chan->pushbuf_base = start;
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+ chan->pushbuf_base = pb->bo.mem.mm_node->start << PAGE_SHIFT;
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} else
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if (dev_priv->card_type != NV_04) {
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ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
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dev_priv->fb_available_size,
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NV_DMA_ACCESS_RO,
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NV_DMA_TARGET_VIDMEM, &pushbuf);
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- chan->pushbuf_base = start;
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+ chan->pushbuf_base = pb->bo.mem.mm_node->start << PAGE_SHIFT;
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} else {
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/* NV04 cmdbuf hack, from original ddx.. not sure of it's
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* exact reason for existing :) PCI access to cmdbuf in
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@@ -61,7 +66,7 @@ nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan)
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dev_priv->fb_available_size,
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NV_DMA_ACCESS_RO,
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NV_DMA_TARGET_PCI, &pushbuf);
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- chan->pushbuf_base = start;
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+ chan->pushbuf_base = pb->bo.mem.mm_node->start << PAGE_SHIFT;
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}
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ret = nouveau_gpuobj_ref_add(dev, chan, 0, pushbuf, &chan->pushbuf);
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